Taiwan's Nanya Completes Own 20nm 8GB DDR4 DRAM | CTIMES

[Martian2]

Not true. Taiwanese Government routinely blocks engagement of Chinese firms for leading edge technology. Chinese investments in MediaTek were disallowed.



Yes, but the bulk of the market soon moves towards higher technology.

And the leading edge technology has higher profit margins which can be reinvested back to develop technology.

Chinese direct investment in MediaTek is not the same as a joint-venture. For example, Taiwan's UMC has joint-venture manufacturing plants on mainland China.

Another method is Taiwan's TSMC 16nm semiconductor fabrication plant on mainland China, which is direct ownership.

A third method is to hire key engineers from Taiwan's Nanya Technology to design China's own 20nm DDR4 DRAM memory chip.

Once a technology appears on Taiwan, these are the three common methods for China to quickly acquire similar technological capability.

1. Joint-venture between Taiwanese tech company and a mainland Chinese company
2. Taiwanese company builds a subsidiary direct-ownership semiconductor manufacturing plant on mainland China
3. Mainland China hires key engineers from a Taiwanese tech company

 

[AndrewJin]

Chinese direct investment in MediaTek is not the same as a joint-venture. For example, Taiwan's UMC has joint-venture manufacturing plants on mainland China.

Another method is Taiwan's TSMC 16nm semiconductor fabrication plant on mainland China, which is direct ownership.

A third method is to hire key engineers from Taiwan's Nanya Technology to design China's own 20nm DDR4 DRAM memory chip.

Once a technology appears on Taiwan, these are the three common methods for China to quickly acquire similar technological capability.

1. Joint-venture between Taiwanese tech company and a mainland Chinese company
2. Taiwanese company builds a subsidiary direct-ownership semiconductor manufacturing plant on mainland China
3. Mainland China hires key engineers from a Taiwanese tech company

Talents are flocking to mainland like no tomorrow....

 

[TaiShang]

Talents are flocking to mainland like no tomorrow....

And it is a good thing for both sides.

After all, all of those talents flocking back to the Mainland are the descendants of those who flocked to Taiwan island over the past six centuries.

1. Joint-venture between Taiwanese tech company and a mainland Chinese company
2. Taiwanese company builds a subsidiary direct-ownership semiconductor manufacturing plant on mainland China
3. Mainland China hires key engineers from a Taiwanese tech company

 

[cirr]

step by step, together

紫光国芯：计划明年推出首款国产DDR4内存

2017-12-29 09:33:43

观察者此前曾报道，紫光集团官网2月12日消息，总投资300亿美元（约2063亿人民币）紫光南京半导体产业基地和总投资300亿元人民币的紫光IC国际城项目正式宣布开工。该基地主要产品为3D-NAND FLASH、DRAM存储芯片等，占地面积约1500亩。建成后，这将是中国规模最大的芯片制造工厂，月产量将达10万片。

紫光集团认为该项目将有力地支撑我国在主流存储器领域的跨越式发展，帮助中国解决芯片这项被称为“工业粮食”的核心问题。

紫光集团董事长赵卫国 图自视觉中国

12月19日至21日，紫光控股以8632万港元（约7213万人民币）的总价，合计增持联想控股292万股，超过5%的举牌线。12月23日，在停止增持联想控股的第二天，紫光控股又以近5000万港元（约4178万人民币）增持中芯国际。紫光未来在半导体行业的布局与芯片国产化等方面或许将有更加出色的表现。

我国半导体市场需求在全球占比名列榜首，但国内企业竞争力却有限，产品供需缺口较大，CPU及存储芯片更是几乎完全依赖于进口，存储芯片已经成为我国半导体产业受外部制约最严重的基础产品之一，因此存储芯片国产化也成为我国半导体发展大战略中的重要一步。

 

[Dungeness]

CCP-KMT secret agreement to make China great again?

I wish KMT could remain relevant in future cross-strait relationship, but it seems it has lost its purpose.

 

[gambit]

No. It doesn't matter. The difference between 20nm and 10nm is marginal (only "a 30% productivity gain").

My new computer uses DDR4 20nm DRAM. There was no need to pay a premium for 10nm DRAM.

If I want more memory, I buy more 20nm DRAM at a reasonable price. 10nm is sought by cutting-edge buyers who are willing to pay a premium. That is not the BULK of the market.

As usual -- you do not know what you are talking about.

Die shrink is inevitable. The reason for structural shrinkage is to create more dies per wafer. Companies that cannot shrink loses market share and money to those that can. Once a shrink is proven in functional and reliability testing, whatever remaining lines of the previous generation will be completed and the next wafer start will be of the new shrink. So by the time you are ready for your own increase in memory, you will have no choice other than the latest shrink.

 

[大汉奸柳传志]

step by step, together

紫光国芯：计划明年推出首款国产DDR4内存

2017-12-29 09:33:43

观察者此前曾报道，紫光集团官网2月12日消息，总投资300亿美元（约2063亿人民币）紫光南京半导体产业基地和总投资300亿元人民币的紫光IC国际城项目正式宣布开工。该基地主要产品为3D-NAND FLASH、DRAM存储芯片等，占地面积约1500亩。建成后，这将是中国规模最大的芯片制造工厂，月产量将达10万片。

紫光集团认为该项目将有力地支撑我国在主流存储器领域的跨越式发展，帮助中国解决芯片这项被称为“工业粮食”的核心问题。

紫光集团董事长赵卫国 图自视觉中国

12月19日至21日，紫光控股以8632万港元（约7213万人民币）的总价，合计增持联想控股292万股，超过5%的举牌线。12月23日，在停止增持联想控股的第二天，紫光控股又以近5000万港元（约4178万人民币）增持中芯国际。紫光未来在半导体行业的布局与芯片国产化等方面或许将有更加出色的表现。

我国半导体市场需求在全球占比名列榜首，但国内企业竞争力却有限，产品供需缺口较大，CPU及存储芯片更是几乎完全依赖于进口，存储芯片已经成为我国半导体产业受外部制约最严重的基础产品之一，因此存储芯片国产化也成为我国半导体发展大战略中的重要一步。

Righteous. Say goodbye to Samsung

 

[Martian2]

As usual -- you do not know what you are talking about.

Die shrink is inevitable. The reason for structural shrinkage is to create more dies per wafer. Companies that cannot shrink loses market share and money to those that can. Once a shrink is proven in functional and reliability testing, whatever remaining lines of the previous generation will be completed and the next wafer start will be of the new shrink. So by the time you are ready for your own increase in memory, you will have no choice other than the latest shrink.

Baloney.

Your simplistic claim that the most leading-edge technology wins and non-leading edge loses is flat-out not true.

Taiwan's United Microelectronics Corporation (world's third largest foundry) derives the majority of its revenues from 28nm. It had a $400 million profit in 2015.

Taiwan's TSMC (world's largest foundry) possesses leading-edge technology at 16nm. However, it also derived the majority of its revenues from the previous-generation 28nm when 20nm was available.

In the real world, leading edge technology is only ONE factor. Price of the technology is an equally important factor. A third factor is the amount of time necessary to develop a new product based on leading-edge technology. Reliability is a fourth factor.

To claim that leading-edge technology automatically outweighs all of the OTHER FACTORS is stupid and wrong.

I'm going to keep buying 20nm DDR4 ram memory chips until 10nm DDR4 ram is cheaper per gigabyte. For the majority of consumers, PRICE is the deciding factor. I don't care that 10nm is better technology than 20nm.

 

[gambit]

Taiwan's TSMC (world's largest foundry) possesses leading-edge technology at 16nm. However, it also derived the majority of its revenues from the previous-generation 28nm when 20nm was available.

As usual, you do not know what you are talking about.

When a manufacturer continues to produce a certain shrink, it does so UNDER CONTRACT.

If I use a certain die shrink, I do it because I did my own testing and is confident of its reliability and performance under my usage for that die shrink. But that does not mean I do not use the new shrink for other purposes. A major reason is code optimization that exploits each specific die shrink because of the reduction in physical dimensions of the discrete devices. Each shrink increases performance, even at the figure that you ( ignorantly ) sneered at back in post 13.

Let us take Intel/Micron PCM 3D Crosspoint technology for an example of those code changes...

https://www.theregister.co.uk/2016/...ry_speed_with_xpoint_and_storageclass_memory/

Although NAND is much faster than disk it is still a great deal slower than memory and the essential coding rule of thumb that says IO is slower than a memory access still stands. It means coders, keen to shorten application run times, will try to restrict the amount of IO that’s carried out, and server/storage system engineers will try to use NAND caching to get over disk data delays, and DRAM caching to get over NAND access delays.

That stack of code is based on disk drive era assumptions in which IO stack traversal time was such a small proportion of the overall IO time that it on its own did not matter. But, with XPoint access time at the single digit microsecond level, stack efficiency becomes much more important.

Device shrink technology determine code optimization. A mere %5 reduction in data transfer speed inside a NAND cell can mean a %20 increase in read/write operations. A %20 increase in read/write operations can mean -- for the NYSE -- a few additional billion$ per day in trading.

https://software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview

...application developers may need to adapt their code to optimize it with the changed cache hierarchy on the Intel Xeon processor Scalable family of processors.

And YOU, a nobody on an anonymous Internet forum, sneered at a %30 increase in productivity ?

So if I use a previous shrink it is only because I have a specific need for it. Today, I know for a fact that if a customer ask, Micron will start up an expired line like SROM for a premium price. In fact, I know that ALL manufacturer keeps recipes for everything they ever made just in case someone ask for a specific product design, no matter how obsolete.

In the real world,...

Every time I read something from you that says something about 'the real world', I laughs.

You admittedly never had a real job and still living with your parents. WTF do you know about 'the real world' ?

 

[Martian2]

As usual, you do not know what you are talking about.

When a manufacturer continues to produce a certain shrink, it does so UNDER CONTRACT.

If I use a certain die shrink, I do it because I did my own testing and is confident of its reliability and performance under my usage for that die shrink. But that does not mean I do not use the new shrink for other purposes. A major reason is code optimization that exploits each specific die shrink because of the reduction in physical dimensions of the discrete devices. Each shrink increases performance, even at the figure that you ( ignorantly ) sneered at back in post 13.

Let us take Intel/Micron PCM 3D Crosspoint technology for an example of those code changes...

https://www.theregister.co.uk/2016/...ry_speed_with_xpoint_and_storageclass_memory/

Device shrink technology determine code optimization. A mere %5 reduction in data transfer speed inside a NAND cell can mean a %20 increase in read/write operations. A %20 increase in read/write operations can mean -- for the NYSE -- a few additional billion$ per day in trading.

https://software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview

And YOU, a nobody on an anonymous Internet forum, sneered at a %30 increase in productivity ?

So if I use a previous shrink it is only because I have a specific need for it. Today, I know for a fact that if a customer ask, Micron will start up an expired line like SROM for a premium price. In fact, I know that ALL manufacturer keeps recipes for everything they ever made just in case someone ask for a specific product design, no matter how obsolete.


Every time I read something from you that says something about 'the real world', I laughs.

You admittedly never had a real job and still living with your parents. WTF do you know about 'the real world' ?

Everything you just said is irrelevant to my point: 20nm DDR4 RAM memory chips represent the bulk of the market. 10nm is unimportant, because most consumers are unwilling to pay a premium for it.
----------

OFFTOPIC: I co-started five businesses (three restaurants, one export refurbished-semiconductor business, and one electronics small business). I earned my Social Security retirement pay about ten years ago. I've held two jobs at the same time and worked two days straight without sleep.

I am pretty sure that I have a lot more private sector job experience than you do.

One final thing: I live in a tower. My life is pretty comfortable and I'm doing something new right now.

 

[gambit]

Everything you just said is irrelevant to my point: 20nm DDR4 RAM memory chips represent the bulk of the market. 10nm is unimportant, because most consumers are unwilling to pay a premium for it.

As usual, you do not know what you are talking about.

When a die shrink is in bulk production, the next shrink is already under quality and reliability testing. Not research and development, but actually finished device engineering. But also by this time, engineering samples sent to all current customers and potential clients. So for you to say that the next shrink is unimportant because it has a higher price is sheer ignorance and arrogant.

Usually, the next generation do have a higher price point, but that is because of low production rate, but the shrink made up for that precisely because of its smaller size, hence the word 'shrink', which means more dies ( chips ) per wafer out. The consumer really has no choice as the supply of the current shrink eventually go away and the next generation's price declines as production rate increases.

There are unique and extreme cases where a client insists on a previous shrink. NASA is one such case.

https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20100021966.pdf
https://en.wikipedia.org/wiki/Soft_error

The design of error detection and correction circuits is helped by the fact that soft errors usually are localised to a very small area of a chip. Usually, only one cell of a memory is affected, although high energy events can cause a multi-cell upset.

Regardless of memory types such as DRAM or NAND, as structures gets smaller, the cell becomes more vulnerable to 'bit flipping' due to stray cosmic radiation that penetrate the cell and alter its memory state. The client will pay a higher price for the supplier to restart an obsolete product line that according to the client's own testing is more resistant or even immune to soft error via 'bit flipping'.

OFFTOPIC: I co-started five businesses (three restaurants, one export refurbished-semiconductor business, and one electronics small business). I earned my Social Security retirement pay about ten years ago. I've held two jobs at the same time and worked two days straight without sleep.

I am pretty sure that I have a lot more private sector job experience than you do.

One final thing: I live in a tower. My life is pretty comfortable and I'm doing something new right now.

I doubt that.

In previous debates, you admitted that you are still inexperienced in the workforce due to your school work. Now, you claimed to have these business experience and failed to see production rates and price decline relationship ?

Is that federal agent still lurking out there watching you cheering for China on PDF ?

Marty, you are biggest liar on this forum, pal.

 

[Martian2]

As usual, you do not know what you are talking about.

When a die shrink is in bulk production, the next shrink is already under quality and reliability testing. Not research and development, but actually finished device engineering. But also by this time, engineering samples sent to all current customers and potential clients. So for you to say that the next shrink is unimportant because it has a higher price is sheer ignorance and arrogant.

Usually, the next generation do have a higher price point, but that is because of low production rate, but the shrink made up for that precisely because of its smaller size, hence the word 'shrink', which means more dies ( chips ) per wafer out. The consumer really has no choice as the supply of the current shrink eventually go away and the next generation's price declines as production rate increases.

There are unique and extreme cases where a client insists on a previous shrink. NASA is one such case.

https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20100021966.pdf
https://en.wikipedia.org/wiki/Soft_error

Regardless of memory types such as DRAM or NAND, as structures gets smaller, the cell becomes more vulnerable to 'bit flipping' due to stray cosmic radiation that penetrate the cell and alter its memory state. The client will pay a higher price for the supplier to restart an obsolete product line that according to the client's own testing is more resistant or even immune to soft error via 'bit flipping'.


I doubt that.

In previous debates, you admitted that you are still inexperienced in the workforce due to your school work. Now, you claimed to have these business experience and failed to see production rates and price decline relationship ?

Is that federal agent still lurking out there watching you cheering for China on PDF ?

Marty, you are biggest liar on this forum, pal.

Are you retarded? I don't care about the die shrink. That's common knowledge.

My point is that cutting-edge technology sometimes do not confer an automatic market advantage.

Here are three recent examples.

Prohibitive Cost

TSMC has cutting-edge 7nm logic-chip semiconductor fabrication technology. Except for Apple (which is the world's richest consumer electronics company), no other company is currently willing to pay for TSMC's expensive 7nm technology. Qualcomm and MediaTek have both deferred on 7nm, because the development cost is a staggering $271 million.

Qualcomm, MediaTek yet to advance to 7nm node | DigiTimes (December 13, 2017)
"The sources estimated that for a smartphone chipset maker, annual shipments of 120-150 million chips fabricated on 7nm process are required to secure a break-even against the development cost, and only Apple, Samsung, Qualcomm and MediaTek can achieve that."

The Race To 10/7nm | Semiconductor Engineering (May 22, 2017)
"For those who migrate beyond 16nm/14nm, it will require deep pockets. In total, it will cost $271 million to design a 7nm chip, according to Gartner. In comparison, it costs around $80 million to design a 16nm/14nm chip and $30 million for a 28nm planar device, the research firm said."

Samsung is a competitor to every semiconductor and electronics company

Samsung beat TSMC to 10nm logic-chip fabrication technology. No one cared. No major company (except captive Qualcomm because Samsung buys Qualcomm SnapDragon chips) placed an order with Samsung for 10nm logic-chip production.

Samsung Edges TSMC in 10 nm | EE Times (March 22, 2017)
"INDIANAPOLIS — Samsung appears to be about a quarter ahead of Taiwan Semiconductor Manufacturing Co. (TSMC) with the ramp of 10-nm process technology, according to a veteran chip analyst."

United Microelectronics Corporation's (UMC) 14nm logic-chip fabrication technology generated a meager 1% of revenue
UMC offers nearly cutting-edge technology at 14nm. Its customers don't care. They are not willing to pay a premium for 14nm technology. The bulk of UMC's revenues is at 28nm and 40nm.

UMC Reports Second Quarter 2017 Results | Business Wire (July 26, 2017)
"14nm represented 1% of 2Q17 revenue, while 28nm contribution remains at 17%. 40nm accounted for 28% of sales."

Conclusion

In conclusion, COST is a critical factor that determines whether a cutting-edge technology becomes widespread. Samsung has manufactured 10nm DDR4 RAM chips. The problem is cost. 20nm DDR4 RAM chips are cheaper and the bulk of the market will not migrate to 10nm DDR4 RAM for year(s).

Since Samsung is the seller of 10nm DDR4 RAM memory chips, PC manufacturers are far less inclined to buy and install Samsung memory chips in their personal computers. The biggest user of Samsung 10nm DDR4 RAM chips is probably Samsung subsidiaries. We have seen the vast majority of semiconductor and electronics companies try to avoid providing Samsung with revenues, which Samsung will use to compete against them.
----------

OFF-TOPIC: I went back to school for pre-pharmacy or pre-Med. I never said it was the first time I went to college.

 

[gambit]

Are you retarded?

Nope, just smarter and more experienced than you are.

I don't care about the die shrink.

And I do -- because I am actually in the industry.

My point is that cutting-edge technology sometimes do not confer an automatic market advantage.

Here are three recent examples.

Sometimes ?

The examples you brought on do not match that 'sometimes' assertion, pal. All they did was shown a POINT of die shrink where cost is -- for a time -- financially unpalatable since it is standard practice to pass the R/D cost to the buyers.

I doubt that you knew of the phrase 'die shrink' so am going to educate you on another: 'node skipping'.

https://semiengineering.com/to-shrink-or-not-to-shrinkand-how-much/

Node skipping is happening across the semiconductor industry. “We do see a lot of customers looking at the risk versus the reward of going to 20 first, then 14, or skipping 20 and going to 14,” observed Jean-Marie Brunet, product marketing director at Mentor Graphics.

As so often in the past, new technologies, from materials to processing equipment, offers the chance to jump one shrink to a smaller die size where the cost is more attractive.

OFF-TOPIC: I went back to school for pre-pharmacy or pre-Med. I never said it was the first time I went to college.

Hey...Your lie, tell it your way. You portrayed yourself as a stock market player, bodybuilder, and now going to be doctor. A modern day renaissance man.

Kid, for as long as I have been in this industry, the one thing I have learned is never to make a definitive statement the kind you made as you tries to portray yourself as 'knowledgeable' in this forum.

Now...Just in case you think I am a bullshitter like you are...

Next to your post is a fully formed 12-in NAND wafer. Each die is 128gb in capacity. The wafer is functionally dead as it was stress tested in temperature, voltage, and current. Then there are fancy math algorithms to say each design ID is rated for A/B/C performance, etc...etc...

For a long time, the industry is struggling to transition to 450 mm, or 18-in, wafers. I am currently on a business trip in Orlando, Fl, testing various wafer handling robots, hence the wafers that travels with me. We will be interviewing 4 vendors.

Cheer for China all you want. But stay out of subjects you know nothing about.

 

[Han Patriot]

Nope, just smarter and more experienced than you are.


And I do -- because I am actually in the industry.


Sometimes ?

The examples you brought on do not match that 'sometimes' assertion, pal. All they did was shown a POINT of die shrink where cost is -- for a time -- financially unpalatable since it is standard practice to pass the R/D cost to the buyers.

I doubt that you knew of the phrase 'die shrink' so am going to educate you on another: 'node skipping'.

https://semiengineering.com/to-shrink-or-not-to-shrinkand-how-much/

As so often in the past, new technologies, from materials to processing equipment, offers the chance to jump one shrink to a smaller die size where the cost is more attractive.


Hey...Your lie, tell it your way. You portrayed yourself as a stock market player, bodybuilder, and now going to be doctor. A modern day renaissance man.

Kid, for as long as I have been in this industry, the one thing I have learned is never to make a definitive statement the kind you made as you tries to portray yourself as 'knowledgeable' in this forum.

Now...Just in case you think I am a bullshitter like you are...

Next to your post is a fully formed 12-in NAND wafer. Each die is 128gb in capacity. The wafer is functionally dead as it was stress tested in temperature, voltage, and current. Then there are fancy math algorithms to say each design ID is rated for A/B/C performance, etc...etc...

For a long time, the industry is struggling to transition to 450 mm, or 18-in, wafers. I am currently on a business trip in Orlando, Fl, testing various wafer handling robots, hence the wafers that travels with me. We will be interviewing 4 vendors.

Cheer for China all you want. But stay out of subjects you know nothing about.

I have a 12" slice in my room too. So?

 

[shadows888]

Nope, just smarter and more experienced than you are.


And I do -- because I am actually in the industry.


Sometimes ?

The examples you brought on do not match that 'sometimes' assertion, pal. All they did was shown a POINT of die shrink where cost is -- for a time -- financially unpalatable since it is standard practice to pass the R/D cost to the buyers.

I doubt that you knew of the phrase 'die shrink' so am going to educate you on another: 'node skipping'.

https://semiengineering.com/to-shrink-or-not-to-shrinkand-how-much/

As so often in the past, new technologies, from materials to processing equipment, offers the chance to jump one shrink to a smaller die size where the cost is more attractive.


Hey...Your lie, tell it your way. You portrayed yourself as a stock market player, bodybuilder, and now going to be doctor. A modern day renaissance man.

Kid, for as long as I have been in this industry, the one thing I have learned is never to make a definitive statement the kind you made as you tries to portray yourself as 'knowledgeable' in this forum.

Now...Just in case you think I am a bullshitter like you are...

Next to your post is a fully formed 12-in NAND wafer. Each die is 128gb in capacity. The wafer is functionally dead as it was stress tested in temperature, voltage, and current. Then there are fancy math algorithms to say each design ID is rated for A/B/C performance, etc...etc...

For a long time, the industry is struggling to transition to 450 mm, or 18-in, wafers. I am currently on a business trip in Orlando, Fl, testing various wafer handling robots, hence the wafers that travels with me. We will be interviewing 4 vendors.

Cheer for China all you want. But stay out of subjects you know nothing about.

your in like every industry on like every different subject in different threads. i'm curious, maybe you're just a pathological liar?

 

[AndrewJin]

your in like every industry on like every different subject in different threads. i'm curious, maybe you're just a pathological liar?

Never believe in viet