China's 28nm DUV lithography machine was delivered in 2021

[gambit]

The advantage is in density as shown in the teardown, being able to separately optimize production for each wafer, and being able to outsource the CMOS dies to a foundry so they can dedicate more productive capability to their core IP of the NAND array. It also has thermal budget advantages.

If it wasn't useful Samsung wouldn't be thinking of doing the same thing, as your own source states.

Did Samsung Just Endorse YMTC’s Xtacking? - The Memory Guy Blog

During his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me. He spoke favorably of the approach that YMTC is using to produce 3D NAND flash. This approach, which YMTC named "Xtacking," involves the use of two separate wafers to manufacture a 3D NAND...

thememoryguy.com

And nobody said they were groundbreaking, you were the one that said their products are "pseudo 3D". What's not 3D about the memory array? What's pseudo about it, does the product function and is it 3D?

Sure...

You build two houses. The first house contains the living room, the kitchen, the dining area, the master bedroom, one master bathroom, one 1/2 bathroom, and the standard 2-car garage. The second house contains three bedrooms and two bathrooms. Then you stack the second house atop the first house. Any architect or homebuilder would say that cosmetically and functionally, it is a two-story house, but they would also say you did not design and built a true two-story house.

 

[FairAndUnbiased]

Sure...

You build two houses. The first house contains the living room, the kitchen, the dining area, the master bedroom, one master bathroom, one 1/2 bathroom, and the standard 2-car garage. The second house contains three bedrooms and two bathrooms. Then you stack the second house atop the first house. Any architect or homebuilder would say that cosmetically and functionally, it is a two-story house, but they would also say you did not design and built a true two-story house.

Lol if it's so bad why is Samsung looking to use the same technology? And from your own source too. Let's get real here if Micron used this you'd be here explaining how this is the future of 3D NAND and is clearly the best architecture possible.

 

[gambit]

Lol if it's so bad why is Samsung looking to use the same technology? And from your own source too. Let's get real here if Micron used this you'd be here explaining how this is the future of 3D NAND and is clearly the best architecture possible.

First, I never said it was bad, I only pointed out the truth of what YMTC did.

Second, the goal was to get to market with a version, any version, of '3D NAND' as fast possible, so YMTC did the best way they know how. If YMTC's processes are able to build on a single wafer, they would have because logistically, you cannot deny the points I made in post 120, and it did not take much thought to point out those issues.

So, where do you think the mating step of the controller and memory arrays take place? In fab or post fab? The CMOS array is easy to build by itself so it is better to build it yourself instead of having a foundry contract do it. You said that YMTC can outsource the CMOS array, fair enough, but now there are an additional logistical and technical escape points that are outside your control that raise the risk of excursions. In post 120, those escape points are already in-house where your responses can be more immediate for any problems.

 

[FairAndUnbiased]

First, I never said it was bad, I only pointed out the truth of what YMTC did.

Second, the goal was to get to market with a version, any version, of '3D NAND' as fast possible, so YMTC did the best way they know how. If YMTC's processes are able to build on a single wafer, they would have because logistically, you cannot deny the points I made in post 120, and it did not take much thought to point out those issues.

So, where do you think the mating step of the controller and memory arrays take place? In fab or post fab? The CMOS array is easy to build by itself so it is better to build it yourself instead of having a foundry contract do it. You said that YMTC can outsource the CMOS array, fair enough, but now there are an additional logistical and technical escape points that are outside your control that raise the risk of excursions. In post 120, those escape points are already in-house where your responses can be more immediate for any problems.

you said the NAND array was psuedo 3D and attained by stacking dies. That's not how the NAND array is made. The NAND array is made the same way as everything other NAND array, as a 3D structure on a single wafer. When people say 3D NAND, the 3D portion, that is, the N layer portion, is understood to be the NAND array.

Samsung can already build on 1 wafer. Why would they put CMOS on array as part of their future tech development plan if Samsung's single wafer process is absolutely superior? Clearly there are technical merits to separating the CMOS production and array production.

There's the strong possibility that YMTC is limited by capacity and available equipment, so if they outsource the CMOS portion, they can focus their available equipment on the array portion which is part of their critical IP along with the wafer bonding.

 

[gambit]

you said the NAND array was psuedo 3D and attained by stacking dies. That's not how the NAND array is made. The NAND array is made the same way as everything other NAND array, as a 3D structure on a single wafer. When people say 3D NAND, the 3D portion, that is, the N layer portion, is understood to be the NAND array.

The context of '3D NAND' includes controller, meaning the finished product including the CMOS array, not its components. The 'die stacking' is about the CMOS and the memory arrays.

Samsung can already build on 1 wafer. Why would they put CMOS on array as part of their future tech development plan if Samsung's single wafer process is absolutely superior? Clearly there are technical merits to separating the CMOS production and array production.

There's the strong possibility that YMTC is limited by capacity and available equipment, so if they outsource the CMOS portion, they can focus their available equipment on the array portion which is part of their critical IP along with the wafer bonding.

3D NAND's Vertical Scaling Race

More competition, business uncertainty, and much more difficult manufacturing processes when 3D NAND scales vertically.

semiengineering.com

The device also has a 30% smaller die size than other chips. To accomplish this feat, Micron pioneered a concept called CMOS-under-array, where it stacks the 3D NAND array over the peripheral logic.​

​

Others have different approaches. Some develop separate memory array and logic dies, which are situated next to each other. Going forward, though, most are moving toward the CMOS-under-array concept to reduce the die sizes. “One easily overlooked characteristic of 3D flash is that it boosted the write performance of NAND up by a factor of ~three compared to 2D flash,” said Johann Alsmeier, a senior director at Western Digital, in a presentation at IEDM. “The main reason is the simpler program methods possible due to the complete screening of the NAND channels in the gate-all-around structure and the larger cell geometry with lower programming noise. Even higher parallelism can be achieved with multi-plane CUA (CMOS-under-array) architectures, of four or more partly independent planes for read and write. However, the CUA process is more costly if used for very low number of WLs.”​

If Samsung want to have separate lines for their 3D NAND processes, it would be for economic reasons, as highlighted.

The CuA design is technically and logistically more complex which equals to longer processing time but it gives the manufacturer greater quality controls, and if there are manufacturing errors, the single line can be stopped and all wafers more quickly contained, even post fab. By 'post fab', I mean outside of the non-electrical testing steps, not literally outside of the facility. The electrical testing steps are in Probe which contains Functional and Parametric. If there are separate memory and CMOS arrays lines, Probe must wait until both dies are mated before they can do anything. ParamEngs can do some in-line structural verification of both arrays, but they must closely monitor each line to select their sampling materials. FuncEngs can do nothing until the wafer arrive at Probe.

The CuA design is unitary. Technically and logistically more complex. Longer manufacturing time. But better controlled.

What YMTC is doing, and Samsung contemplating, spread the processing time over two lines where one line is faster than the other. One line is under someone else's supervision. And combined the entire process have increased risks of uncaught errors.

 

[FairAndUnbiased]

The context of '3D NAND' includes controller, meaning the finished product including the CMOS array, not its components. The 'die stacking' is about the CMOS and the memory arrays.

3D NAND's Vertical Scaling Race

More competition, business uncertainty, and much more difficult manufacturing processes when 3D NAND scales vertically.

semiengineering.com

The device also has a 30% smaller die size than other chips. To accomplish this feat, Micron pioneered a concept called CMOS-under-array, where it stacks the 3D NAND array over the peripheral logic.​

​

Others have different approaches. Some develop separate memory array and logic dies, which are situated next to each other. Going forward, though, most are moving toward the CMOS-under-array concept to reduce the die sizes. “One easily overlooked characteristic of 3D flash is that it boosted the write performance of NAND up by a factor of ~three compared to 2D flash,” said Johann Alsmeier, a senior director at Western Digital, in a presentation at IEDM. “The main reason is the simpler program methods possible due to the complete screening of the NAND channels in the gate-all-around structure and the larger cell geometry with lower programming noise. Even higher parallelism can be achieved with multi-plane CUA (CMOS-under-array) architectures, of four or more partly independent planes for read and write. However, the CUA process is more costly if used for very low number of WLs.”​

If Samsung want to have separate lines for their 3D NAND processes, it would be for economic reasons, as highlighted.

The CuA design is technically and logistically more complex which equals to longer processing time but it gives the manufacturer greater quality controls, and if there are manufacturing errors, the single line can be stopped and all wafers more quickly contained, even post fab. By 'post fab', I mean outside of the non-electrical testing steps, not literally outside of the facility. The electrical testing steps are in Probe which contains Functional and Parametric. If there are separate memory and CMOS arrays lines, Probe must wait until both dies are mated before they can do anything. ParamEngs can do some in-line structural verification of both arrays, but they must closely monitor each line to select their sampling materials. FuncEngs can do nothing until the wafer arrive at Probe.

The CuA design is unitary. Technically and logistically more complex. Longer manufacturing time. But better controlled.

What YMTC is doing, and Samsung contemplating, spread the processing time over two lines where one line is faster than the other. One line is under someone else's supervision. And combined the entire process have increased risks of uncaught errors.

there's also technical advantages to wafer bonding approaches, such as a possible improve in the thermal budget of the chip based on the Samsung interview you posted. based on a reading of your source, limitations of high aspect ratio RIE and wafer warpage were addressed.

1. RIE for 128 layers CUA takes a long time to etch down through all 128 layers and as you keep building layers, to get wordlines to the CMOS portion you have to progressively etch - and fill - 128 layer trenches.

2. wafer warpage is a problem for highly stacked thin films due to differential stress between the deposition layers and the substrate.

It's plausible to me that wafer bonding the CMOS to the array helps solve some of these problems, such as being able to deposit the memory array directly on new substrate rather than a heterogeneously patterned CMOS array (each topped with materials of different lattice constant) would help reduce differential stress between the array and substrate. It's plausible to me that there could be a reduction of 128 layer RIE etches required. These are process details we're not privy to, but I wouldn't write it off as merely being easier yet more expensive.

so I'm not going to just say that YMTC took the easy way out or for economics (because the wafer bonding does add 1 more step and does cost more, according to your source). there were likely compelling technical reasons.

 

[gambit]

there's also technical advantages to wafer bonding approaches, such as a possible improve in the thermal budget of the chip based on the Samsung interview you posted. based on a reading of your source, limitations of high aspect ratio RIE and wafer warpage were addressed.

1. RIE for 128 layers CUA takes a long time to etch down through all 128 layers and as you keep building layers, to get wordlines to the CMOS portion you have to progressively etch - and fill - 128 layer trenches.

2. wafer warpage is a problem for highly stacked thin films due to differential stress between the deposition layers and the substrate.

It's plausible to me that wafer bonding the CMOS to the array helps solve some of these problems, such as being able to deposit the memory array directly on new substrate rather than a heterogeneously patterned CMOS array (each topped with materials of different lattice constant) would help reduce differential stress between the array and substrate. It's plausible to me that there could be a reduction of 128 layer RIE etches required. These are process details we're not privy to, but I wouldn't write it off as merely being easier yet more expensive.

so I'm not going to just say that YMTC took the easy way out or for economics (because the wafer bonding does add 1 more step and does cost more, according to your source). there were likely compelling technical reasons.

Items 1 and 2 treads into proprietary information, specifically the recipes themselves.

Wafer warpage WILL be detected with in-line parametric testing provided the effects of each layer are known. With warpage, the die's structures will not be uniform and that will result in predictable binning at functional testing, but if the warpage is detected with in-line parametric measurement, the warped wafer should not pass one subsequent step where the warpage was detected.

https://www.researchgate.net/publication/253217972_Using_an_Intelligent_Approach_to_Recognize_a_Wafer_Bin_Map_Pattern

To decrease cost, semiconductor manufacturing companies always aim for yield enhancement. The analysis of Wafer Bin Maps (WBMs) is important for yield improvement. Real data sets are collected from a famous semiconductor manufacturing company to verify the presented method. Four types of WBMs patterns, center, edge, local, and ring types are selected for verification. Experimental results showed that with adequate parameter settings, the method can successfully recognize the pattern types and distinguish between random and systematic WBMs. There were 17 testing samples, and 16 of them were recognized correctly. The accuracy was 94.12%.​

This is not new.

1- First, a failed bins pattern is detected at Functional.

2- Next, a sample of dies, failed and good, are sent to SEM analyses.

3- Next, the dissected dies revealed common structures that caused one bin, common structures that caused another bin, and so on.

4- Next, Parametric engineers develop an in-line sampling regime at precisely the fab steps that produced the warped wafer.

5- Last, fab process owners alter their recipes to eliminate or at least reduce the warpage.

The cycle repeat until Functional no longer detect the fail binnings or if the percentage of failed dies are acceptable, the failed dies will be scrapped at extraction.

If YMTC and Samsung uses the separate lines method for their 3D NAND products from fear of wafer warpage, that is their problem.

 

[silverox]

I hope that SMIC can win the technology war. I spent 400,000 RMB to buy SMIC's stock, and I lost 300,000 RMB. I was deeply trapped. It was the United States that caused my economic loss.

 

[Song Hong]

There are a lot of 2nd hand DUV around. Most IC is not 7nm. 14 nm is good enough for 99% of IC by production and 50% by revenue.