Indeed, just having any 100% domestic components stepper is mind boggling, something no other country in the world ever did, if it's really true...
Three points:
- The lion share of Chinese ICs are 90nm+, and we have to go to Taiwanese to make those
There is already a domestic capability for economic 180nm tapeouts that a regular business can go for, but a lot of businesses are still choosing TSMC, or other foreign fabs just for quality of client service, and SPEEED
CanSemi for example is just starting, they have some bad feedback, but they don't seem to mind as they have a giant market of clients whose only immediate need is to put "Made in China" label on their ICs to make money.
When they will be beating Taiwanese on both service, and cost. Then we can talk.
For now, having Chinese foundries that can offer mainstream 300mm service is a way more immediate need that having own equipment.
If relations with Taiwan will seriously sour tomorrow, we will not be able to even make own discreet ICs, simple things like opamps, pmics, simple RF parts, and etc in sufficient volume.
- The entirety of Chinese domestic market for <65nm parts is not that big if you count the number of companies. You have 20 behemoth sized clients who can afford 65nm, and everybody else goes for 90nm+
Just not so many of our companies manufacture high speed logic, nor have huge ICs. 300mm wafers make 90nm manufacturing quite economical.
Even at 90nm, a one megagate design will be taking more area for bonding pads than for the IC itself. This is why advanced packaging is such a money saver.
If you can do fan out in plastic, you put 4-6 times more small sized ICs on a wafer even with an ancient 90nm process.
Mainstream ICs simply don't gain anything from <65nm nodes. IC manufacturing is not all about feature size. Things like materials, cell design rules, backend features, and tons of other things industry outsiders have never heard of in their life are equally, or more important than feature size for the mainstream customer.
- As I said before many times, the lion share of mid-tier digital logic below 1ghz will stay at 40nm and 65nm for a very long time. Why? Because 65nm, and 40nm nodes are the last nodes where you can reliably use dry tools, and single patterning. For anything else, yield management, and cycle times begin to conflict with each other.
Therefore, I propose to focus on essentials first before chasing the bleeding edge, and to avoid the serious mistake the state backed semi companies have done doing the later.
Develop the 65nm planar process for dry tool, single exposure use, with focus on general purpose mixed signal designs. Provide rapid cycle times, and equipment utilisation.
Develop 40nm 3D process for immersion tool, single exposure use, with focus on mainstream digital ICs. Provide low power consumption, and developer friendliness.
While developing the litho capability, seek blue ocean opportunities more relevant in Chinese market: high volume maskless tech for things like smart interposers; Memory in the backend; Novel material devices; Advanced packaging; Power-on-Chip tech; etc.
P.S. I completely forgot one very important thing: photomask manufacturing. This is another are where we have near no domestic expertise. All advanced photomasks in China are coming from TW, and Japan. For example, you can't get phase shift photomasks here, nor advanced inspection, or repair.