No, they are not, and I worked for/with two of those three, and you can guess which two. TSMC excels at mass manufacturing. Tech nodes for mass manufacturing of commodity products are not the same as tech nodes at specialized niche products, which often must be done at higher nodes due to design requirements. Not always, just often. Micron have a history of keeping decades old recipes on hand, and NASA contractors often called Micron.
The annual capacity of the manufacturing facilities managed by TSMC and its subsidiaries exceeded 12 million 12-inch equivalent wafers in 2020. These facilities include four 12-inch wafer GIGAFAB® fabs, four 8-inch wafer fabs, and one 6-inch wafer fab – all in Taiwan – as well as one 12-inch...
www.tsmc.com
The annual capacity of the manufacturing facilities managed by TSMC and its subsidiaries exceeded 12 million 12-inch equivalent wafers in 2020. These facilities include four 12-inch wafer GIGAFAB® fabs, four 8-inch wafer fabs, and one 6-inch wafer fab – all in Taiwan – as well as one 12-inch wafer fab at a wholly owned subsidiary, TSMC Nanjing Company Limited, and two 8-inch wafer fabs at wholly owned subsidiaries, WaferTech in the United States and TSMC China Company Limited.
Fabs do not run 12 in wafers on a whim. Three hundred mm wafers have unique klompications and many customers do not want to risk with their commodity product lines, such as NAND use in the typical USB drives. On the other hand, SRAM is structurally complex to manufacture but is also a commodity product, so if a customer
DEMANDS that TSMC uses 200 mm wafers for a specific product, TSMC must accommodate, if they want the contract.
Because the circuit structure of each DRAM basic memory unit is very simple, DRAM has low power consumption and low price. In this way, DRAM chips with large storage capacity can be manufactured at low cost. However, its disadvantage is that slow speed of reading and writing (capacitor needs to charge and discharge continuously) affects the performance of DRAM.
On the contrary, the structure of SRAM is more complex, which consists of six MOSs. We can label them with M1, M2, M3, M4, M5 and M6, respectively. These six MOSs need to be combined together in order to store one bit of data.
In fact, a client can even demand a foundry to build a wafer on a specific tech nodes, no matter how old. So just because TSMC is able to go down to 3 nanos on one or two lines, that does not mean others are 'behind' TSMC because they do not have their own fabs that can go down to that level. They may have made their stuff at 3 nanos at their own fabs, refined the process, and asked if TSMC can meet requirements.
As far as this news story go, the idea that China will seize hard assets is reasonable since China already violated IP left and right. If the CCP feels hard pressed enough, seizing foreign hard assets will be seen as justifiable.