Hamartia Antidote
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http://www.electronicsweekly.com/ne...core-multi-cluster-designs-384-cores-2016-10/
Evolved from the existing I6400 and called I6500, the 64bit CPU can be used to coherently implement configurations of CPU cores within a cluster – ‘heterogeneous inside’ – as well as a variety of configurations of CPU clusters and GPU or accelerator clusters – ‘heterogeneous outside’.
“I6500 builds on the real-time hardware virtualisation capability pioneered in the MIPS I6400 core,” said Imagination. “Designers can consolidate multiple CPU cores with a single core and dynamically and deterministically allocate CPU bandwidth per application.”
Up to four threads per core can be implemented, and up to six cores per cluster, and up to 64 clusters can be implemented together for a total of 384 cores and 1,536 threads.
heterogeneous inside a cluster
heterogeneous outside a cluster
ACE-coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators,” said Imagination.
Mobileye has already licensed it for its EyeQ5 central computer chip for sensor fusion in fully autonomous vehicles (expected in 2020).
EyeQ5 will have eight multi-threaded MIPS CPU cores coherently coupled with eighteen cores of Mobileye’s own ‘vision processors’.
Application is expected in driver assistance systems (ADAS), autonomous vehicles, networking, drones, industrial automation, security, video analytics and machine learning.
It is available for licensing now, with general availability expected in Q1 2017.
Evolved from the existing I6400 and called I6500, the 64bit CPU can be used to coherently implement configurations of CPU cores within a cluster – ‘heterogeneous inside’ – as well as a variety of configurations of CPU clusters and GPU or accelerator clusters – ‘heterogeneous outside’.
“I6500 builds on the real-time hardware virtualisation capability pioneered in the MIPS I6400 core,” said Imagination. “Designers can consolidate multiple CPU cores with a single core and dynamically and deterministically allocate CPU bandwidth per application.”
Up to four threads per core can be implemented, and up to six cores per cluster, and up to 64 clusters can be implemented together for a total of 384 cores and 1,536 threads.
heterogeneous inside a cluster
- shared low latency L2 cache
- 8 coherent ports
- up to 6 CPUs + 2 IO coherence units (IOCUs) – or up to 8 IOCUs
- dual-issue multi-threaded CPU cores
- up to 4 threads/core (24 thread/cluster)
- virtualisation – up to 31 secure execution domains
- I/O MMU for virtualisation of IO resources
- virtualised GIC – allocates interrupts to specific execution domains
- up to 4 auxiliary AXI ports (non-coherent)
- low-latency peripherals
- cluster-level (or multi-cluster) SPRAM
- ACE bus for coherence between clusters
heterogeneous outside a cluster
- up to non-identical 64 clusters (NoC- dependent)
- CPUs clusters can be combined with ACE-compatible GPU (eg PowerVR)
- CPUs clusters can be combined with accelerator clusters
ACE-coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators,” said Imagination.
Mobileye has already licensed it for its EyeQ5 central computer chip for sensor fusion in fully autonomous vehicles (expected in 2020).
EyeQ5 will have eight multi-threaded MIPS CPU cores coherently coupled with eighteen cores of Mobileye’s own ‘vision processors’.
Application is expected in driver assistance systems (ADAS), autonomous vehicles, networking, drones, industrial automation, security, video analytics and machine learning.
It is available for licensing now, with general availability expected in Q1 2017.
