ICube UPU, the next step in processor evolution?

[Martian2]

You must be joking, right? Or are you really that daft? It is not that difficult to find the basic wafer process flow...

How is a Wafer Fabricated / Wafer Fabrication Procedure?

But even so, every design is slightly different in the process flow. The fact that you use the word 'chip' when you are talking at the wafer level is immediately suspect. The word 'chip' is used either for popular media distribution or when a media reporter/commentator uses it himself/herself. No one who works at the wafer level uses the word 'chip' when describing his work. No one who works at the wafer level uses the word 'chip' when the word 'die' is appropriate.

I don't want a link to wafer fabrication procedure. I want you to answer my question on the main problem that you face. Do you understand the distinction?

Why not use the word "chip?" I use it all the time. I'm not writing a formal paper. I was baking chips. Do you seriously think all physicists use the word "mass" instead of "weight"? I use the word weight all the time too. You seem to have some strange preconceptions. Correct terminology is only for official reports.

Pick one of my questions:

1. After the wafers have finished baking, what do you do next? Describe the procedure and reasons.

2. While you are in the process of making a chip, what is probably your biggest worry and how do you solve it?

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If you find both questions to be too hard, I'll give you a third choice.

3. When you make a mistake in baking your chip, can you save it? Explain your answer.

 

[gambit]

I don't want a link to wafer fabrication procedure. I want you to answer my question on the main problem that you face. Do you understand the distinction?

Why not use the word "chip?" I use it all the time. I'm not writing a formal paper. I was baking chips. Do you seriously think all physicists use the word "mass" instead of "weight"? I use the word weight all the time too. You seem to have some strange preconceptions. Correct terminology is only for official reports.

Pick one of my questions:

1. After the wafers have finished baking, what do you do next? Describe the procedure and reasons.

2. While you are in the process of making a chip, what is probably your biggest worry and how do you solve it?

----------

If you find both questions to be too hard, I'll give you a third choice.

3. When you make a mistake in baking your chip, can you save it? Explain your answer.

You really think that anyone who is involved in the wafer fabrication process must know in details every single step? If this is a 'gotcha' tactic, it failed. I work in Probe, which is the final step after the wafer has finished processing. But if you want play this 'gotcha' game, then explain what is 'InLine Param', who can request it, why, and how is this different than 'Final Param'. If you cannot answer, then it is evident for everyone to see how absurd what you are trying to do.

 

[Martian2]

You really think that anyone who is involved in the wafer fabrication process must know in details every single step? If this is a 'gotcha' tactic, it failed. I work in Probe, which is the final step after the wafer has finished processing. But if you want play this 'gotcha' game, then explain what is 'InLine Param', who can request it, why, and how is this different than 'Final Param'. If you cannot answer, then it is evident for everyone to see how absurd what you are trying to do.

I have asked you three times now. You have refused to answer any of the three general questions that I have presented. You have no idea what you're talking about and I grow weary of your nonsense.

These are simple questions that anyone, who has ever fabricated chips, could easily answer in a couple of paragraphs. However, obviously not you.

If you don't know the answers, just say "I don't know." Stop beating around the bush. It's pathetic.

These are not "gotcha" questions. They are general questions, where you are free to explain your reasoning. You haven't even made an attempt.

Don't forget, you challenged me on whether I had actually baked chips. I am simply proving that I know a lot more about fabricating chips than you do. You got yourself into this mess.

 

[gambit]

I have asked you three times now. You have refused to answer any of the three questions that I have presented. You have no idea what you're talking about and I grow weary of your nonsense.

Ah...So now you do not like it when the table is turned. Only one year of baking wafers and pretense of what you are talking about will do that for you. What you described is nothing more than what a Production line operator would do.

FYI, the 'InLine Param' step is practically mandatory in every memory design to verify PARAMETRIC integrity of a recipe, be it matured product or new designs, especially new designs. Any design or Quality Assurance engineer can request said step. Not every 'lot' or wafer (quartz) boat must go through said step. Recipe or process deviations can trigger a request for the 'InLine Param' step to assess the extent of the excursion and to verify if the corrective actions were effective. In short, anything can trigger a request for the 'InLine Param' step and it can be done at any intra-steps during the wafer processing flow. The 'Final Param' step is used to verify the same Parametric criteria AFTER the lot completed processing. Said lot can be sampled instead of full. New products will demand full. And I have not even touch 'Final Probe' yet.

I do not need to know how Production handled the wafers, I just need to know the flow in general. If you do not know what I am talking about, may be whatever design/process/recipe you worked on long ago does not need it. May be because it was not sophisticated enough to need such verification.

 

[Martian2]

Ah...So now you do not like it when the table is turned. Only one year of baking wafers and pretense of what you are talking about will do that for you. What you described is nothing more than what a Production line operator would do.

FYI, the 'InLine Param' step is practically mandatory in every memory design to verify PARAMETRIC integrity of a recipe, be it matured product or new designs, especially new designs. Any design or Quality Assurance engineer can request said step. Not every 'lot' or wafer (quartz) boat must go through said step. Recipe or process deviations can trigger a request for the 'InLine Param' step to assess the extent of the excursion and to verify if the corrective actions were effective. In short, anything can trigger a request for the 'InLine Param' step and it can be done at any intra-step during the wafer processing flow. The 'Final Param' step is used to verify the same Parametric criteria AFTER the lot completed processing. Said lot can be sampled instead of full. New products will demand full. And I have not even touch 'Final Probe' yet.

I do not need to know how Production handled the wafers, I just need to know the flow in general. If you do not know what I am talking about, may be whatever design/process/recipe you worked on long ago does not need it. May be because it was not sophisticated enough to need such verification.

Okay, I can see that you have never baked a chip from design to finished product in your life. You've wasted my time. Your earlier post implied you knew more about chip fabrication than I do. Clearly, you have no experience in making chips.

By the way, the third question was a trick question. It didn't matter whether you answered "yes" or "no." Your answer would have been wrong. The answer is actually "yes" and "no." You have to qualify your answer.

If you find both questions to be too hard, I'll give you a third choice.

3. When you make a mistake in baking your chip, can you save it? Explain your answer.

 

[gambit]

These are simple questions that anyone, who has ever fabricated chips, could easily answer in a couple of paragraphs. However, obviously not you.

If you don't know the answers, just say "I don't know." Stop beating around the bush. It's pathetic.

These are not "gotcha" questions. They are general questions, where you are free to explain your reasoning. You haven't even made an attempt.

Heck, I doubt that you would know where CMP is located.

Don't forget, you challenged me whether I had actually baked chips. I am simply proving that I know a lot more about fabricating chips than you do. You got yourself into this mess.

Nope, I challenged that you know enough about the industry to make the sort of claims you did.

---------- Post added at 12:50 AM ---------- Previous post was at 12:48 AM ----------

Okay, I can see that you have never baked a chip from design to finished product in your life. You've wasted my time. Your earlier post implied you knew more about chip fabrication than I do. Clearly, you have no experience in making chips.

By the way, the third question was a trick question. It didn't matter whether you answered "yes" or "no," your answer would have been wrong. The answer is acutally "yes" and "no" and you have to qualify your answer.

Yeah...To 'bake a chip'. Sorry, but I can say the same about you since you certainly have no clue of what I was talking about. So yes, you definitely tried to play a pathetic game of 'gotcha'.

 

[gambit]

3. When you make a mistake in baking your chip, can you save it? Explain your answer.

Please...Save your trick question. The answer is 'Depends' on where the mistake occurs. Take over-etch, for example, with larger geometries, there is a margin of physical safety that a wafer can be recovered and re-etch, but that went away with the 30s scaling.

And just in case you think am making this 'InLine Param' thing up...

Notice the abstract alone confirmed everything I said: Systematic variation patterns from die-to-die and from wafer-to-wafer. Or that of process uncertainty, as in new recipe/process for matured products or new products themselves. Process uncertainty is another phrasing for errors.

 

[ptldM3]

Is anyone familiar with the Quad-zentri-WU? I heard it is the future.

 

[qwerrty]

AMD future generation chip will be unifed cpu like what i-cube is doing right now. no time table when it will come out.

AMD Fusion System Architecture Moves to Unify CPUs and GPUs

*ttp://www.extremetech.com/computing/87326-amd-fusion-system-architecture-moves-to-unify-cpus-and-gpus

 

[Oy.vey]

SMIC imports foreign equipments from IBM to make 40nm fab. Do you know what that means? Without foreign assistance, China cannot do it on its own. China's 40nm fab is not indigenous. China's first 65nm photolithography machine was only unveiled in mid 2011.

You do know that TSMC, UMC and Globalfoundries are simply pure play fabs that relies on imported machines for making ICs right? It is the same case with SMIC. Even Samsung, which does most of its design in-house, requires equipment from elsewhere. ASML, Nikon and Canon dominate the market for such machines, despite not being IC manufacturers themselves.

You can say the same for Intel, Nvidia and so on. You or Martian are conflating the matter of fab ownership/capacity and tooling manufacturers. Regardless of who owns their own fab or the machines they license, it doesn't change the fact that the design is indigenous and while not absolutely cutting edge, indigenous fab capabilities is the least of their concerns right now.

 

[marshall]

AMD future generation chip will be unifed cpu like what i-cube is doing right now. no time table when it will come out.

The CPU and GPU will still be distinct on the AMD Fusion. ICube UPU integrates the CPU/CPU into a homogeneous core with shared registers, instruction set, etc. That's why an entire support ecosystem needs to be built from scratch while AMD already has it. The ICube UPU looks like it's best chance of success lies with the smart phone & tablet markets. Supposedly they have ported Android over and are now working on hardware support with some mobile partners.

I read somewhere that the ICube is massively scalable and more suitable for parallel computing than all existing processors. So, its efficiency does not drop off as severely as other processors the more you use, as in you could put thousands of these cores together and they would behave efficiently. This would suggest that it would be great for cloud computing and supercomputers. Sounds alot like tile nodes on a single enormous shared cache with crossbar interconnect which China is already working on with the Godson-T processor. Seems like hype with the limited information but interesting. If there's any truth to this, then I think there's more to the ICube processor than its mobile application.

 

[qwerrty]

Sounds alot like tile nodes on a single enormous shared cache with crossbar interconnect which China is already working on with the Godson-T processor. Seems like hype with the limited information but interesting. If there's any truth to this, then I think there's more to the ICube processor than its mobile application.

this godson-t, 64 core processor?

 

[marshall]

this godson-t, 64 core processor?

Yup, the same. The speculation was that since the 1st iteration of ICube UPU on the 65nm process with 2 cores came in at 2.7mm2 that it would be around 1mm2 with 4 cores on the 2nd iteration at 40nm. Basically, it would be relatively easy to have 100 cores on the same die on a crossbar interconnect all sharing a huge L2 cache with a single memory controller. This sort of simplicity makes parallel processing on a MASSIVE scale...as in millions of cores... very very interesting considering the relative thread efficiency compared to how other processors are integrated into supercomputers today. The similarity of this hypothesis to the Godson-T is my own because the Godson-T is already designed this way other than the interleaved L2 cache + memory controllers at the 4 corners of the die and the much more powerful processing potential of each individual ICube UPU core.

Btw, do you know the status of the Godson-T 16-core samples? Godson-T research is supposedly to determine the most efficient and effective methods of integrating cores for fine grained thread level processing. If this is true, then there will never be a commercial counterpart to the Godson-T research project but instead some of China's various CPU/UPU cores will be modified to allow the sort of topology as decided by the Godson-T for their future supercomputers.

ps. Why does the picture of the Godson-T have the "Taiwan" stamp on it considering it was fabbed at SMIC?

 

[qwerrty]

the one that fab by SMIC is a 16 core, 130nm sample. the picture above is 64 core prototype. ICT also has another version of godson-t in testing capable of 1,000+ concurrent threads processing.

 

[marshall]

the one that fab by SMIC is a 16 core, 130nm sample. the picture above is 64 core prototype. ICT also has another version of godson-t in testing capable of 1,000+ concurrent threads processing.

You are more current than I am with the Godson-T status. Do you have links referencing the 64-core and simulation of the prototype capable of 1000+ threads? Pretty impressive progress! Last time I read up about the Godson-T, was around 9 months ago and at that time, they were still doing simulations on the 16-core variant. Congrats to the developers, impressive.