Hey thanks for your answer. But there is small issue I wanna remind. Actually 32 nm was that generation's standard node size and 28 nm was the stop gap.
SPIE | Proceeding | Challenges for the 28nm half node: Is the optical shrink dead?
GlobalFoundries: 32nm and 28nm under way, moving away from strict SOI | Chips | Geek.com
IBM, GlobalFoundries move to 28nm process tech- The Inquirer
And this second issue is that of course the smaller the node is it's much more energy efficient and better. But there are a lot of companies out there which made their designs for 32 nm and most of them won't be able to easily adapt 28 nm technology. Of course 28 nm is more advanced, but as you've mentioned there are a lot of IC designers that doesn't work cutting edge. Actually SMIC owes a lot to it's robust 40 nm and 65 nm technology for it's current surge in revenues and profit.
MOQ is another issue for many small companies out there as well. They sometimes work with bigger nodes to have lower MOQ's. Most of the time small companies can't afford large MOQ's for cutting edge nodes.
Here's an interview with SMIC's CEO Tzu-Yin Chiu,
In the midst of SMIC's financial achievements, Chiu last week received the coveted Environment, Health, and Safety (EHS) leadership award from SEMI, the global semiconductor industry association.
With breathing room at last, SMIC now talks about the company's various milestones in its environmental, safety, and philanthropy activities. Chiu touched upon a "SMIC Liver Transplant Program for Children," an initiative launched last year to contribute 2 million RMB to fund liver transplants for impoverished children in China.
During a one-on-one interview with EE Times last week, Chiu didn't hesitate to express SMIC's interest in expansion -- beyond China.
Asked about IBM fabs that may be up for sale, as Big Blue executes its plan to withdraw from the semiconductor business, Chiu said he's interested. "Never rule out the possibility," he said. However, he quickly added, "Of course, we are aware of some of the issues... IBM is, after all, the jewel of the United States."
SMIC is rehabilitated. China's leading foundry's operation is much more stable. The company is building its revenue and profit growth based on, not a wild, but a modest, capacity buildup of 6.7% per year.
But is this all we can expect? Is this as high as SMIC gets?
SMIC's critics worry that SMIC, under Chiu's leadership, might have already given up the dream of directly competing with the world's Tier 1 foundries such as Taiwan Semiconductor Manufacturing Co. (TSMC), Samsung, and Intel.
One long-time semiconductor industry observer based in Shanghai, who spoke on the condition of anonymity, told EE Times, "The gap between SMIC and TSMC is not narrowing, but rather, widening larger in the last few years."
Indeed, while leading fab owners are busy talking about a 14 nm process node, SMIC says its 28 nm process node is "now frozen," allowing potential customers to test and verify SMIC's newest node.
If this is not a concern for SMIC, what other priorities does the company have in mind? How will SMIC compete in the long run?
EE Times recently sat down with SMIC's CEO in its Shanghai headquarters. Here's an edited version of that Q&A.
EE Times: Some in the industry are worried that the technology gap between SMIC and other leading foundries is widening. What's your view?
Tzu-Yin Chiu: Probably not with TSMC... but I think we are narrowing our technology gap with other foundries. We are keeping pace with the industry, and we are quite confident of the progress we're making.
EE Times: What other foundries are you referring to?
Chiu: I'd rather not name names.
EE Times: Help me understand with which specific technologies you think you are narrowing the gap with your competitors.
Chiu: For one, we're very happy with our 40nm/45nm ramp. In 2013, 40nm/45nm revenue contribution was more than $200 million. [SMIC's 45/40 nanometer revenue increased significantly, to account for 16% of the revenue in the second half of 2013.]
Second, our 28nm node technology for both high-k metal gate (HKMG) and POLY/SiON processes were frozen by the end of 2013. Through our Multi-Project Wafer offering, we're entertaining commercial ICs and customer product verification. We are getting very good feedback.
SMIC's technology nodes by percentage
(Source: SMIC)
EE Times: How big is your 28 nm capacity?
Chiu: Beijing will be our main 28 nm fab, where we will have a capacity of 6,000 wafers per month by the end of the third quarter this year. We're moving our equipment to Beijing as we speak. But we also have a capacity in Shanghai, capable of addressing the 28 nm technology.
With Beijing and Shanghai combined, our 28 nm capacity is 15,000 wafers per month.
EE Times: Is that enough?
Chiu: It all depends on the needs of our customers. As you know, our 28 nm process technology is fungible. In other words, those new 28 nm process lines are also capable of 40 nm products. Our plan is that over the next three years, we will build our Beijing facility to have a capacity of 35,000 wafers per month.
EE Times: What do you have to do in order to make that happen?
Chiu: We need to bring in customers and ramp up our technology. [SMIC already did the first Multi-Project Wafer (MPW) late last year. The company is planning on four more MPW shuttles in 2014.]
We also need to make sure that there is enough capital for full ramp-up to 35,000 wafers per month.
SMIC's 28 nm technology milestones
(Source: SMIC)
EE Times: I understand that your Beijing project is 55 percent funded by SMIC and 45 percent by other JV shareholders. You previously said that you're spending about $570 million for your new Beijing project. Is your Beijing fab sufficiently funded?
Chiu: Yes, we're getting what we need, and we're confident of it. This is well within our means.
EE Times: I've been hearing about the Chinese government's strong interest in investing really big money into the domestic semiconductor industry -- over the next five to 10 years -- as part of the nation's initiative to encourage innovation and advance its economy. I'd imagine SMIC could be a big beneficiary of that.
Chiu: We'd welcome the policy to encourage investment in semiconductors. But we are not aware of any details.
EE Times: We all agree about the stability and focus you've brought to SMIC. What were three major factors that you think contributed to the company's steady growth last year?
Chiu: This has been a result of the efforts by the whole team.
But first, I should point out that the successful ramp-up of new technology -- namely, 40nm/45nm processes -- contributed to our revenue in the past year.
Second, our differentiated technology in such areas as CMOS image sensors, power management ICs, and embedded non-volatile memory. All three differentiated technologies combined, we achieved an average of more than 40 percent growth in revenue.
Third, robust growth in China contributed to our success. Forty percent of our revenue comes from Chinese customers.
EE Times: Now that we have begun to hear about the pending merger among Chinese fabless companies, such as the one between Spreadtrum and RDA, are we going to see the number of your Chinese customers decline?
Chiu: We see some Chinese companies are breaking off the pack. We're engaged with all the winners.
EE Times: What about customers outside China?
Chiu: We are going global. We have new engagements all over the world. We have top US fabless companies as our long-term customers over the last 10 years. They're silent, but they're very persistent customers. Among those moving from 40 nm to 28 nm, some are top 10 global fabless companies.
EE Times: How's your CMOS image sensor business going?
Chiu: You know that we have a backside illumination platform for our CMOS image sensors. [BSI is a special way of arranging the imaging elements to increase the amount of light captured, thus improving low-light performance. In essence, it removes the readout circuitry and interconnects from the light path, and illuminates the sensor from the backside.]
With the rise of "selfies," 2 megapixel sensors are in big demand for the front camera of a cellphone. They're in high-volume production now. Our customers' demand for 5 megapixel and 8 megapixel image sensors has grown rapidly.
EE Times: Previously, you talked about the Chinese government's mandate, under which magnetic cards will change to IC cards in 2015. Our understanding is that SMIC developed an embedded EEPROM platform, which had been adopted by a majority of China's bankcard IC design houses. What's the latest?
Chiu: Four out of six UnionPay-qualified bank cards use our platform. Most of our customers are verifying their products, and small-volume production will begin in the second half of this year. A more significant ramp-up and revenue contribution are expected in 2015.
EE Times: How's SMIC's plan for MEMS?
Chiu: SMIC has a very successful program with Silicon Labs on CMEMS [designed to allow direct post-processing of high-quality MEMS layers on top of Silicon Labs' RF/mixed-signal CMOS technology.]
EE Times: But that's mainly for manufacturing CMEMS-based MEMS oscillators. What about other MEMS?
Chiu: Our plan is to closely work with our customers to develop proprietary MEMS process technology. We also have our own capable MEMS teams and a set of MEMS capabilities on our own.
EE Times: What are those?
Chiu: We're not ready to reveal specifics. But our plan is to use our new fab where both CMOS image sensors and MEMS can be manufactured. Our goal is to leverage a part of the special tools required for CMOS image sensor production for MEMS.
EE Times: What new fab?
Chiu: We're actually building a new CMOS Image Sensor [CIS] ecosystem. Our plan is to use this ecosystem for both CIS and MEMS.
First, we already have the 28nm/40nm front-end facility in Shanghai.
Second, we established a joint venture with Toppan. With Toppan, we manufacture on-chip color filters and micro lenses for CMOS image sensors.
Last October, SMIC formed an R&D and manufacturing center dedicated to vision, sensors, and 3D IC, with a mission to consolidate manufacturing capabilities for silicon-based sensors, thru-silicon-via [TSV] technology and other middle-end wafer process [MEWP] technologies.
Then, just last month, we announced a new JV with Jiangsu Changjiang Electronics Technology Co. Ltd., China's largest backend house. The new JV will be responsible for 12-inch bumping and related testing. JCET will also build advanced back-end package production lines nearby.
So, all told, we will be leveraging the network of CIS ecosystem for MEMS as well.
* * *
The SMIC CEO said that SMIC must make sure it meets the needs of the Chinese market and Chinese products. For that matter, in responding to Chinese customers' strong demand for 8-inch displays, SMIC is now bringing up an 8-inch fab in Shenzhen. "We have procured the second-hand equipment, and we're installing them right now," Chiu said. The plan is to build a capacity of 50,000 wafers per month. "Our specialty technology products will be made at the 8-inch fab. They include PMIC and image sensors."
Clearly, SMIC;s focus today is what China needs right now. But what about high-end advanced technology? Should I even ask about SMIC's plan for 14 nm process?
Chiu said, "We will be ready with FinFET at 14 nm process by the end of 2016." He said it as a matter of fact. Somehow, he never made it sound like a big deal.
Will SMIC Narrow Tech Gap? | EE Times
He downplayed the 14 nm node in 2016 which actually marks the drop of technological gap between SMIC and tier 1 fabs to 2 years. However he braggs a lot about 40 nm and 65 nm. If this was my company I'd be popping champaigns celebrating 14 nm technology in 2016. However he is so calm about this.
, and help build a platform around its product.
