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TMSC——Taiwan's last fortress
Opinionated - China Chipping Away to Semiconductor Dominance
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JSCh
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IMECAS Developed a New Type of Vertical Gate-All-Around Field-Effect Transistors
Author： Zhu Huilong
Update time： 2019-12-17
Vertical gate-all-around (GAA) devices are considered as important promising candidates to replace FinFETs at and beyond the 2nm technology node. However, the fabrication of vertical GAA field-effect transistors (FETs) faces serious challenges for improving their performance and manufacturability. In IEDM 2018, Dr. Ryckaert1 from IMEC emphasized that the length of the gates and the alignment of the gate to the channel were key challenges for the research and fabrication of vertical GAA devices.
Fortunately, Professor Huilong Zhu started a research project in 2016 to investigate these issues in his research group. A new type of vertical nanowire (NW)/nanosheet (NS) FETs, called Vertical Sandwich Gate-All-Around FETs or VSAFETs in short，was presented and fabricated in Zhu’s Group to overcome the shortcomings of existing vertical devices. The results have been published recently on IEEE Electron Device Letters (DOI: 10.1109/LED.2019.2954537).
In some detail, an isotropic quasi-atomic-layer-etching (qALE) of SiGe selective etching was investigated systematically and applied to fabricate NW/NS channels in epitaxial growth Si/SiGe/Si structures. The precise control of both the channel size and gate length can be achieved by the qALE and the epitaxial growth. Self-aligned HKMG for vertical GAA FETs was obtained for the first time. Importantly, the integration flow for the VSAFETs is compatible with that for state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology. The pVSAFET with a gate-length/NS-thickness of 60 nm/20 nm was obtained. The SS, DIBL, and Ion/Ioff ratio of the device were 86 mV/dec, 40mV and 1.8?105, respectively.
This work was partially supported by the Academy of Integrated Circuit Innovation of Chinese Academy of Sciences (No. Y7YC01X001).
References:
1. J. Ryckaert, "3D integration for density and functionality," in 2018 IEEE International Electron Devices Meeting (IEDM), short course. San Francisco, USA, 2018.
IMECAS Developed a New Type of Vertical Gate-All-Around Field-Effect Transistors----The Institute of Microelectronics of Chinese Academy of Sciences
Author： Zhu Huilong
Update time： 2019-12-17
Vertical gate-all-around (GAA) devices are considered as important promising candidates to replace FinFETs at and beyond the 2nm technology node. However, the fabrication of vertical GAA field-effect transistors (FETs) faces serious challenges for improving their performance and manufacturability. In IEDM 2018, Dr. Ryckaert1 from IMEC emphasized that the length of the gates and the alignment of the gate to the channel were key challenges for the research and fabrication of vertical GAA devices.
Fortunately, Professor Huilong Zhu started a research project in 2016 to investigate these issues in his research group. A new type of vertical nanowire (NW)/nanosheet (NS) FETs, called Vertical Sandwich Gate-All-Around FETs or VSAFETs in short，was presented and fabricated in Zhu’s Group to overcome the shortcomings of existing vertical devices. The results have been published recently on IEEE Electron Device Letters (DOI: 10.1109/LED.2019.2954537).
In some detail, an isotropic quasi-atomic-layer-etching (qALE) of SiGe selective etching was investigated systematically and applied to fabricate NW/NS channels in epitaxial growth Si/SiGe/Si structures. The precise control of both the channel size and gate length can be achieved by the qALE and the epitaxial growth. Self-aligned HKMG for vertical GAA FETs was obtained for the first time. Importantly, the integration flow for the VSAFETs is compatible with that for state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology. The pVSAFET with a gate-length/NS-thickness of 60 nm/20 nm was obtained. The SS, DIBL, and Ion/Ioff ratio of the device were 86 mV/dec, 40mV and 1.8?105, respectively.
This work was partially supported by the Academy of Integrated Circuit Innovation of Chinese Academy of Sciences (No. Y7YC01X001).
References:
1. J. Ryckaert, "3D integration for density and functionality," in 2018 IEEE International Electron Devices Meeting (IEDM), short course. San Francisco, USA, 2018.
IMECAS Developed a New Type of Vertical Gate-All-Around Field-Effect Transistors----The Institute of Microelectronics of Chinese Academy of Sciences
JSCh
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Chinese company releases self-developed MMW chips; will boost 5G
By Yin Yeping Source:Global Times Published: 2020/1/21 20:18:41
Millimeter wave phased array antenna. Photo: Courtesy of Xphased
China's self-developed millimeter wave (MMW) phased array chip will be put into mass production in February with low-cost silicon technology, the chip's research team said. An industry expert said that its low cost will greatly boost popularization of 5G in China and beyond.
Industry experts believe that the technology breakthrough that enables mass production of the 5G MMW phased array chip will effectively launch the product into the global market at a reasonable price and with a better performance.
The chip, unveiled to the public on Sunday, was jointly developed by Chengdu Xphased Technology Co (Xphased), Purple Mountain Laboratories, and a research team from Southeast University in Nanjing, East China's Jiangsu Province.
Zhang Chengjun, general manager of Xphased, told the Global Times on Tuesday that the company has significantly reduced its production cost and made commercialization possible, and mass production of the MMW chips is expected to start on February 1.
"In the past, MMW chips in III-V compound semiconductors were priced at several hundred or even thousands of yuan. Given these high prices, it is basically impossible to commercialize chips," Zhang said.
"The new chip has a much lower price compared with the same kind of chips in the global market, but the quality of the new chip is at world-class levels," he said.
The innovation project involving the MMW chip was initiated in March 2016. After some years of research and development, small-scale trial production began last October, and 50,000 chips were made.
Xphased has already received orders from companies worldwide, including some in France, and it is discussing with companies in the US about future deals regarding phased-array chips and antennas, Zhang said.
The launch of the chip is a late-stage advantage for China's 5G development, Zhao Dixian, a professor at Southeast University, told the Global Times.
"Currently, China is using centimeter-wave frequencies bands for telecommunications. MMW frequencies provide much more bandwidth for mobile communication, and therefore provide faster communication speeds," Zhao said, adding that if a centimeter wave is a single lane, the MMW involves multiple lanes.
However, some believed that although it is an important step toward 5G development, challenges remain.
"The mass production of MMW chips is surely an indispensable part of the popularization of 5G in China, but it's not all," Xiang Ligang, a veteran industry analyst told the Global Times on Tuesday.
"To achieve 5G popularization, other elements such as coding, core networks and software management also need to take place," he said, adding that it will still take some time before the popularization of 5G.
By Yin Yeping Source:Global Times Published: 2020/1/21 20:18:41
China's self-developed millimeter wave (MMW) phased array chip will be put into mass production in February with low-cost silicon technology, the chip's research team said. An industry expert said that its low cost will greatly boost popularization of 5G in China and beyond.
Industry experts believe that the technology breakthrough that enables mass production of the 5G MMW phased array chip will effectively launch the product into the global market at a reasonable price and with a better performance.
The chip, unveiled to the public on Sunday, was jointly developed by Chengdu Xphased Technology Co (Xphased), Purple Mountain Laboratories, and a research team from Southeast University in Nanjing, East China's Jiangsu Province.
Zhang Chengjun, general manager of Xphased, told the Global Times on Tuesday that the company has significantly reduced its production cost and made commercialization possible, and mass production of the MMW chips is expected to start on February 1.
"In the past, MMW chips in III-V compound semiconductors were priced at several hundred or even thousands of yuan. Given these high prices, it is basically impossible to commercialize chips," Zhang said.
"The new chip has a much lower price compared with the same kind of chips in the global market, but the quality of the new chip is at world-class levels," he said.
The innovation project involving the MMW chip was initiated in March 2016. After some years of research and development, small-scale trial production began last October, and 50,000 chips were made.
Xphased has already received orders from companies worldwide, including some in France, and it is discussing with companies in the US about future deals regarding phased-array chips and antennas, Zhang said.
The launch of the chip is a late-stage advantage for China's 5G development, Zhao Dixian, a professor at Southeast University, told the Global Times.
"Currently, China is using centimeter-wave frequencies bands for telecommunications. MMW frequencies provide much more bandwidth for mobile communication, and therefore provide faster communication speeds," Zhao said, adding that if a centimeter wave is a single lane, the MMW involves multiple lanes.
However, some believed that although it is an important step toward 5G development, challenges remain.
"The mass production of MMW chips is surely an indispensable part of the popularization of 5G in China, but it's not all," Xiang Ligang, a veteran industry analyst told the Global Times on Tuesday.
"To achieve 5G popularization, other elements such as coding, core networks and software management also need to take place," he said, adding that it will still take some time before the popularization of 5G.
JSCh
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Semiconductor industry on steady track despite outbreak
By Ma Si | China Daily | Updated: 2020-02-20 09:16
Employees perform tests on semiconductor chips at the production facility of a Nanchang, Jiangxi province-based high-tech company on Feb 13. [Photo/Xinhua]
Epidemic will not alter the long-term momentum of the sector, says a report
The novel coronavirus outbreak will have a limited impact on China's semiconductor industry since most local wafer manufacturing plants are operating normally and chip design companies can choose remote work to mitigate the fallout from the epidemic, the companies concerned and analysts said.
The chip packaging and test business may be affected to some extent due to the labor shortage, they added.
Semiconductor Manufacturing International Co, the top contract chip manufacturer in the Chinese mainland, said on Friday the company will double its capital spending and expects revenue to grow more than 10 percent this year despite the epidemic.
Zhao Haijun, co-CEO of SMIC, said at an earnings call that all of the company's factories which are mainly located in Shanghai, Beijing and Tianjin are running at full capacity.
The comments came after the company had organized a work group before the Spring Festival holiday to ensure that plants could stay open, while protecting the safety of employees and following government regulations.
"SMIC needs to ensure that factory production runs 365 days a year, 24 hours a day to meet customers' fabrication needs," the company said in a statement.
Fang Jing, chief electronics analyst at Cinda Securities, said most wafer manufacturing plants are dust-free, which makes them less vulnerable to virus infection. It is also a common practice in the industry to keep the highly-automated plants running all year round.
Located in the badly hit city of the contagion outbreak, the Wuhan, Hubei province-based Yangtze Memory Technologies Co Ltd also said its production and operations are proceeding normally and in an orderly manner.
The company has enacted certain isolation measures and partitions to ensure the safety of employees. It is also striving to coordinate with multiple sides to maintain the supply of industrial production materials and logistics services to ensure the sustainability of its businesses, YMTC said in a statement.
Most chip design companies have also resumed operations, with most employees working remotely from their homes.
Shanghai-based HiSilicon, the chip arm of Huawei Technologies Co, said it has already restarted operation. It added that it is pouring resources into maintaining normal operations while preventing its employees from getting infected by the virus.
Unisoc Technologies Co, a core chip subsidiary of Tsinghua Unigroup, said its employees have also gone back to work, with its plants running non-stop since the Lunar New Year holiday.
Though logistics services have been affected by the novel coronavirus outbreak, the company said that it is working hard to solve the problem.
Allwinner Technology, a chip design company based in Zhuhai, Guangdong province, also said it has resumed operations, and shipped a batch of new products last week.
Analysts said the epidemic is partly harming the chip packaging business.
Fang of Cinda Securities said unlike wafer manufacturing plants which run non-stop year round, chip packaging factories usually are closed during the Spring Festival for maintenance work on their equipment.
Taiwan-based chip packing and test company AES said recently the lack of available labor is the biggest problem for its mainland branches. Traffic restrictions during the outbreak make it difficult for many employees who have gone home for the holidays to return to work.
Even if they manage to return, they have to go through the process of health examinations and a seven to 14-day quarantine period.
Another factor is that the first quarter is usually the off-season for the semiconductor industry, which provides a cushion of time for its companies.
AES said despite all the difficulties, 60 to 70 percent of its employees in its plants in the Chinese mainland were on duty during the Spring Festival holiday.
By the end of February, the proportion is expected to reach 80 percent to 85 percent, and by the end of the first quarter, all of its employees will have returned to work, the company said.
JCET Group, another Chinese chip packaging and test company, said earlier this month that its production and operations remain stable. Due to abundant orders during the Spring Festival, only few employees of the company's plant in Jiangyin, Jiangsu province, had gone home for the holidays.
The company said it currently has enough stocks of industrial production material to meet demand. It added it is working closely with government agencies and supply partners to see how to get more raw materials to meet future demand.
Western Securities said in a report that the outbreak will not alter the long-term, strong momentum of China's semiconductor sector.
The upcoming large-scale rollout of 5G networks and the push of China's tech giants to cultivate local chip suppliers have combined to inject fresh vitality into the industry.
China will still build its 5G networks this year. The demand may be delayed by the virus, but it will not vanish, Fang of Cinda Securities explained.
By Ma Si | China Daily | Updated: 2020-02-20 09:16
Epidemic will not alter the long-term momentum of the sector, says a report
The novel coronavirus outbreak will have a limited impact on China's semiconductor industry since most local wafer manufacturing plants are operating normally and chip design companies can choose remote work to mitigate the fallout from the epidemic, the companies concerned and analysts said.
The chip packaging and test business may be affected to some extent due to the labor shortage, they added.
Semiconductor Manufacturing International Co, the top contract chip manufacturer in the Chinese mainland, said on Friday the company will double its capital spending and expects revenue to grow more than 10 percent this year despite the epidemic.
Zhao Haijun, co-CEO of SMIC, said at an earnings call that all of the company's factories which are mainly located in Shanghai, Beijing and Tianjin are running at full capacity.
The comments came after the company had organized a work group before the Spring Festival holiday to ensure that plants could stay open, while protecting the safety of employees and following government regulations.
"SMIC needs to ensure that factory production runs 365 days a year, 24 hours a day to meet customers' fabrication needs," the company said in a statement.
Fang Jing, chief electronics analyst at Cinda Securities, said most wafer manufacturing plants are dust-free, which makes them less vulnerable to virus infection. It is also a common practice in the industry to keep the highly-automated plants running all year round.
Located in the badly hit city of the contagion outbreak, the Wuhan, Hubei province-based Yangtze Memory Technologies Co Ltd also said its production and operations are proceeding normally and in an orderly manner.
The company has enacted certain isolation measures and partitions to ensure the safety of employees. It is also striving to coordinate with multiple sides to maintain the supply of industrial production materials and logistics services to ensure the sustainability of its businesses, YMTC said in a statement.
Most chip design companies have also resumed operations, with most employees working remotely from their homes.
Shanghai-based HiSilicon, the chip arm of Huawei Technologies Co, said it has already restarted operation. It added that it is pouring resources into maintaining normal operations while preventing its employees from getting infected by the virus.
Unisoc Technologies Co, a core chip subsidiary of Tsinghua Unigroup, said its employees have also gone back to work, with its plants running non-stop since the Lunar New Year holiday.
Though logistics services have been affected by the novel coronavirus outbreak, the company said that it is working hard to solve the problem.
Allwinner Technology, a chip design company based in Zhuhai, Guangdong province, also said it has resumed operations, and shipped a batch of new products last week.
Analysts said the epidemic is partly harming the chip packaging business.
Fang of Cinda Securities said unlike wafer manufacturing plants which run non-stop year round, chip packaging factories usually are closed during the Spring Festival for maintenance work on their equipment.
Taiwan-based chip packing and test company AES said recently the lack of available labor is the biggest problem for its mainland branches. Traffic restrictions during the outbreak make it difficult for many employees who have gone home for the holidays to return to work.
Even if they manage to return, they have to go through the process of health examinations and a seven to 14-day quarantine period.
Another factor is that the first quarter is usually the off-season for the semiconductor industry, which provides a cushion of time for its companies.
AES said despite all the difficulties, 60 to 70 percent of its employees in its plants in the Chinese mainland were on duty during the Spring Festival holiday.
By the end of February, the proportion is expected to reach 80 percent to 85 percent, and by the end of the first quarter, all of its employees will have returned to work, the company said.
JCET Group, another Chinese chip packaging and test company, said earlier this month that its production and operations remain stable. Due to abundant orders during the Spring Festival, only few employees of the company's plant in Jiangyin, Jiangsu province, had gone home for the holidays.
The company said it currently has enough stocks of industrial production material to meet demand. It added it is working closely with government agencies and supply partners to see how to get more raw materials to meet future demand.
Western Securities said in a report that the outbreak will not alter the long-term, strong momentum of China's semiconductor sector.
The upcoming large-scale rollout of 5G networks and the push of China's tech giants to cultivate local chip suppliers have combined to inject fresh vitality into the industry.
China will still build its 5G networks this year. The demand may be delayed by the virus, but it will not vanish, Fang of Cinda Securities explained.
JSCh
ELITE MEMBER
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- Jun 9, 2011
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FEBRUARY 24, 2020
A new transverse tunneling field-effect transistor
by Ingrid Fadelli , Tech Xplore
The transverse tunnelling field-effect transistor’s structure and characteristics. Credit: Xiong et al.
Researchers at the Chinese Academy of Sciences have recently fabricated a transverse tunneling field-effect transistor. This is a semiconductor device that can be used to amplify or switch electrical power or signals, operating through a phenomenon known as quantum tunneling. The new transistor, introduced in a paper published in Nature Electronics, was built using a van der Waals heterostructure, a material with atomically thin layers that do not mix with each other, but are instead attached via van der Waals interactions.
Tunnel field-effect transistors are an experimental type of semiconductor device that operate via a mechanism known as band-to-band tunneling (BTBT). These transistors have a wide range of applications, for instance, in the development of radiofrequency (RF) oscillators or memory components for electronic devices.
In these devices, carriers (i.e., particles carrying an electric charge) typically tunnel through a barrier, heading in the same direction as the total output current. The current in this tunnel contributes directly to the device's overall current.
To operate most effectively, these devices should ideally be built with high-quality interfaces and sharp energy band edges. Two-dimensional van der Waals heterostructures may thus be optimal candidates for their fabrication, as researchers can easily stack different materials on top of each other, resulting in high-quality interfaces and sharp band edges.
To enable high tunneling efficiency in semiconductor devices, researchers must be able to tune the density of states with Fermi-level alignment and conserve momentum from the source to end in the momentum space, without involving phonons. The researchers who carried out the recent study featured in Nature Electronics found that using 2-D black phosphorus (BP) allowed them to do both these things.
"Tunnel devices that exhibit negative differential resistance typically follow an operating principle in which the tunneling current contributes directly to the drive current," the researchers wrote in their paper. "Here, we report a tunneling field-effect transistor made from a black phosphorus/Al2O3/black phosphorus van der Waals heterostructure in which the tunneling current is in the transverse direction with respect to the drive current."
In the transverse tunneling field-transistor created by this team of researchers, the tunneling current can elicit a drastic change in the output current via an electrostatic effect. This ultimately allows the device to attain a tunable negative differential resistance with a peak-to-valley ratio (PVR) of over 100 at room temperatures.
"Our device also exhibits abrupt switching, with a body factor (the relative change in gate voltage with respect to that of the surface potential) that is one-tenth of the Boltzmann limit for conventional transistors across a wide temperature range," the researchers wrote in their paper.
This team of researchers at the Chinese Academy of Sciences demonstrated the feasibility of fabricating highly efficient tunneling field-effect transistors using a vertical van der Waals heterostructure containing BP. In the future, the new device could be integrated in a number of electronics, potentially enhancing the performance of radiofrequency oscillators or multi-valued logic applications.
A new transverse tunneling field-effect transistor | Tech Xplore
A new transverse tunneling field-effect transistor
by Ingrid Fadelli , Tech Xplore
Researchers at the Chinese Academy of Sciences have recently fabricated a transverse tunneling field-effect transistor. This is a semiconductor device that can be used to amplify or switch electrical power or signals, operating through a phenomenon known as quantum tunneling. The new transistor, introduced in a paper published in Nature Electronics, was built using a van der Waals heterostructure, a material with atomically thin layers that do not mix with each other, but are instead attached via van der Waals interactions.
Tunnel field-effect transistors are an experimental type of semiconductor device that operate via a mechanism known as band-to-band tunneling (BTBT). These transistors have a wide range of applications, for instance, in the development of radiofrequency (RF) oscillators or memory components for electronic devices.
In these devices, carriers (i.e., particles carrying an electric charge) typically tunnel through a barrier, heading in the same direction as the total output current. The current in this tunnel contributes directly to the device's overall current.
To operate most effectively, these devices should ideally be built with high-quality interfaces and sharp energy band edges. Two-dimensional van der Waals heterostructures may thus be optimal candidates for their fabrication, as researchers can easily stack different materials on top of each other, resulting in high-quality interfaces and sharp band edges.
To enable high tunneling efficiency in semiconductor devices, researchers must be able to tune the density of states with Fermi-level alignment and conserve momentum from the source to end in the momentum space, without involving phonons. The researchers who carried out the recent study featured in Nature Electronics found that using 2-D black phosphorus (BP) allowed them to do both these things.
"Tunnel devices that exhibit negative differential resistance typically follow an operating principle in which the tunneling current contributes directly to the drive current," the researchers wrote in their paper. "Here, we report a tunneling field-effect transistor made from a black phosphorus/Al2O3/black phosphorus van der Waals heterostructure in which the tunneling current is in the transverse direction with respect to the drive current."
In the transverse tunneling field-transistor created by this team of researchers, the tunneling current can elicit a drastic change in the output current via an electrostatic effect. This ultimately allows the device to attain a tunable negative differential resistance with a peak-to-valley ratio (PVR) of over 100 at room temperatures.
"Our device also exhibits abrupt switching, with a body factor (the relative change in gate voltage with respect to that of the surface potential) that is one-tenth of the Boltzmann limit for conventional transistors across a wide temperature range," the researchers wrote in their paper.
This team of researchers at the Chinese Academy of Sciences demonstrated the feasibility of fabricating highly efficient tunneling field-effect transistors using a vertical van der Waals heterostructure containing BP. In the future, the new device could be integrated in a number of electronics, potentially enhancing the performance of radiofrequency oscillators or multi-valued logic applications.
More information: Xiong Xiong et al. A transverse tunnelling field-effect transistor made from a van der Waals heterostructure, Nature Electronics (2020). DOI: 10.1038/s41928-019-0364-5
A new transverse tunneling field-effect transistor | Tech Xplore
2019 Was the worst year for the industry since 2000. The optimism is undueSemiconductor industry on steady track despite outbreak
By Ma Si | China Daily | Updated: 2020-02-20 09:16
Employees perform tests on semiconductor chips at the production facility of a Nanchang, Jiangxi province-based high-tech company on Feb 13. [Photo/Xinhua]
Epidemic will not alter the long-term momentum of the sector, says a report
The novel coronavirus outbreak will have a limited impact on China's semiconductor industry since most local wafer manufacturing plants are operating normally and chip design companies can choose remote work to mitigate the fallout from the epidemic, the companies concerned and analysts said.
The chip packaging and test business may be affected to some extent due to the labor shortage, they added.
Semiconductor Manufacturing International Co, the top contract chip manufacturer in the Chinese mainland, said on Friday the company will double its capital spending and expects revenue to grow more than 10 percent this year despite the epidemic.
Zhao Haijun, co-CEO of SMIC, said at an earnings call that all of the company's factories which are mainly located in Shanghai, Beijing and Tianjin are running at full capacity.
The comments came after the company had organized a work group before the Spring Festival holiday to ensure that plants could stay open, while protecting the safety of employees and following government regulations.
"SMIC needs to ensure that factory production runs 365 days a year, 24 hours a day to meet customers' fabrication needs," the company said in a statement.
Fang Jing, chief electronics analyst at Cinda Securities, said most wafer manufacturing plants are dust-free, which makes them less vulnerable to virus infection. It is also a common practice in the industry to keep the highly-automated plants running all year round.
Located in the badly hit city of the contagion outbreak, the Wuhan, Hubei province-based Yangtze Memory Technologies Co Ltd also said its production and operations are proceeding normally and in an orderly manner.
The company has enacted certain isolation measures and partitions to ensure the safety of employees. It is also striving to coordinate with multiple sides to maintain the supply of industrial production materials and logistics services to ensure the sustainability of its businesses, YMTC said in a statement.
Most chip design companies have also resumed operations, with most employees working remotely from their homes.
Shanghai-based HiSilicon, the chip arm of Huawei Technologies Co, said it has already restarted operation. It added that it is pouring resources into maintaining normal operations while preventing its employees from getting infected by the virus.
Unisoc Technologies Co, a core chip subsidiary of Tsinghua Unigroup, said its employees have also gone back to work, with its plants running non-stop since the Lunar New Year holiday.
Though logistics services have been affected by the novel coronavirus outbreak, the company said that it is working hard to solve the problem.
Allwinner Technology, a chip design company based in Zhuhai, Guangdong province, also said it has resumed operations, and shipped a batch of new products last week.
Analysts said the epidemic is partly harming the chip packaging business.
Fang of Cinda Securities said unlike wafer manufacturing plants which run non-stop year round, chip packaging factories usually are closed during the Spring Festival for maintenance work on their equipment.
Taiwan-based chip packing and test company AES said recently the lack of available labor is the biggest problem for its mainland branches. Traffic restrictions during the outbreak make it difficult for many employees who have gone home for the holidays to return to work.
Even if they manage to return, they have to go through the process of health examinations and a seven to 14-day quarantine period.
Another factor is that the first quarter is usually the off-season for the semiconductor industry, which provides a cushion of time for its companies.
AES said despite all the difficulties, 60 to 70 percent of its employees in its plants in the Chinese mainland were on duty during the Spring Festival holiday.
By the end of February, the proportion is expected to reach 80 percent to 85 percent, and by the end of the first quarter, all of its employees will have returned to work, the company said.
JCET Group, another Chinese chip packaging and test company, said earlier this month that its production and operations remain stable. Due to abundant orders during the Spring Festival, only few employees of the company's plant in Jiangyin, Jiangsu province, had gone home for the holidays.
The company said it currently has enough stocks of industrial production material to meet demand. It added it is working closely with government agencies and supply partners to see how to get more raw materials to meet future demand.
Western Securities said in a report that the outbreak will not alter the long-term, strong momentum of China's semiconductor sector.
The upcoming large-scale rollout of 5G networks and the push of China's tech giants to cultivate local chip suppliers have combined to inject fresh vitality into the industry.
China will still build its 5G networks this year. The demand may be delayed by the virus, but it will not vanish, Fang of Cinda Securities explained.
JSCh
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China's first 5G microbase station RF chip has been successfully develope
国内首个5G微基站射频芯片YD9601研发成功
2020-03-04 10:24:18 来源 : 科技日报
记者3日从南京经济技术开发区获悉，我国首个5G微基站射频芯片YD9601，在南京宇都通讯科技有限公司经过自主研发流片成功，目前正在进行封装测试。
5G基站分为宏基站和微基站两种。宏基站主要用于室外覆盖，5G微基站主要用于室内，发射功率较小(一般200毫瓦以内)，广泛用于机场高铁等候区域、商业场所、学校医院、园区工厂和社区家庭等场景。5G微基站可以以较低成本有效解决室内覆盖区域的容量(如机场、高铁和商场等热点区域)和覆盖问题(如商业楼宇和家庭)。
“5G微基站射频芯片项目是我们自主研发的有线射频宽带芯片组的拓展。”国家特聘专家、美国麻省理工学院博士王俊峰介绍说，在推出5G微基站射频芯片之前，公司通过研发有线射频宽带HiNOC2.0芯片，拥有了长期的射频芯片技术积累。
据悉，HiNOC2.0是我国下一代有线射频宽带广电接入标准，南京宇都HiNOC2.0射频/基带芯片组可实现600兆每秒的下行速率，完全可与国际巨头的同类产品对标。在中国广播科学研究院进行的标准测试中，搭载这组芯片的设备在85dB的线路衰耗下仍可接入，相比对标的国际巨头同类产品，抗衰减能力提升了10dB左右，这使其更能适应国内复杂、恶劣的网络环境。2019年4月，中国工程院院士倪光南领衔的专家组对HiNOC2.0芯片组进行技术鉴定，认定该芯片组在系统性能上达到了国际同类产品的先进水平，而其中射频芯片部分性能优于国际同类产品。
王俊峰介绍，YD9601不光覆盖700MHz广电频段，也兼容了工信部2月初刚刚颁发许可的3.3—3.4GHz的电信/联通/广电共享室内频段，可以说是为5G时代室内共享微基站量身定做的芯片。
国内首个5G微基站射频芯片YD9601研发成功
2020-03-04 10:24:18 来源 : 科技日报
记者3日从南京经济技术开发区获悉，我国首个5G微基站射频芯片YD9601，在南京宇都通讯科技有限公司经过自主研发流片成功，目前正在进行封装测试。
5G基站分为宏基站和微基站两种。宏基站主要用于室外覆盖，5G微基站主要用于室内，发射功率较小(一般200毫瓦以内)，广泛用于机场高铁等候区域、商业场所、学校医院、园区工厂和社区家庭等场景。5G微基站可以以较低成本有效解决室内覆盖区域的容量(如机场、高铁和商场等热点区域)和覆盖问题(如商业楼宇和家庭)。
“5G微基站射频芯片项目是我们自主研发的有线射频宽带芯片组的拓展。”国家特聘专家、美国麻省理工学院博士王俊峰介绍说，在推出5G微基站射频芯片之前，公司通过研发有线射频宽带HiNOC2.0芯片，拥有了长期的射频芯片技术积累。
据悉，HiNOC2.0是我国下一代有线射频宽带广电接入标准，南京宇都HiNOC2.0射频/基带芯片组可实现600兆每秒的下行速率，完全可与国际巨头的同类产品对标。在中国广播科学研究院进行的标准测试中，搭载这组芯片的设备在85dB的线路衰耗下仍可接入，相比对标的国际巨头同类产品，抗衰减能力提升了10dB左右，这使其更能适应国内复杂、恶劣的网络环境。2019年4月，中国工程院院士倪光南领衔的专家组对HiNOC2.0芯片组进行技术鉴定，认定该芯片组在系统性能上达到了国际同类产品的先进水平，而其中射频芯片部分性能优于国际同类产品。
王俊峰介绍，YD9601不光覆盖700MHz广电频段，也兼容了工信部2月初刚刚颁发许可的3.3—3.4GHz的电信/联通/广电共享室内频段，可以说是为5G时代室内共享微基站量身定做的芯片。
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A small step for atoms, a giant leap for microelectronics
Nature paper reports making and moving large-scale hexagonal boron nitride
HOUSTON – (March 4, 2020) – Step by step, scientists are figuring out new ways to extend Moore’s Law. The latest reveals a path toward integrated circuits with two-dimensional transistors.
Atoms of boron and nitride align on a copper substrate to create a large-scale, ordered crystal of hexagonal boron nitride. The wafer-sized material could become a key insulator in future two-dimensional electronics. Illustration by Tse-An Chen/TSMC
A Rice University scientist and his collaborators in Taiwan and China reported in Nature today that they have successfully grown atom-thick sheets of hexagonal boron nitride (hBN) as two-inch diameter crystals across a wafer.
Surprisingly, they achieved the long-sought goal of making perfectly ordered crystals of hBN, a wide band gap semiconductor, by taking advantage of disorder among the meandering steps on a copper substrate. The random steps keep the hBN in line.
Set into chips as a dielectric between layers of nanoscale transistors, wafer-scale hBN would excel in damping electron scattering and trapping that limit the efficiency of an integrated circuit. But until now, nobody has been able to make perfectly ordered hBN crystals that are large enough — in this case, on a wafer — to be useful.
Brown School of Engineering materials theorist Boris Yakobson is co-lead scientist on the study with Lain-Jong (Lance) Li of the Taiwan Semiconductor Manufacturing Co. (TSMC) and his team. Yakobson and Chih-Piao Chuu of TSMC performed theoretical analysis and first principles calculations to unravel the mechanisms of what their co-authors saw in experiments.
As a proof of concept for manufacturing, experimentalists at TSMC and Taiwan’s National Chiao Tung University grew a two-inch, 2D hBN film, transferred it to silicon and then placed a layer of field-effect transistors patterned onto 2D molybdenum disulfide atop the hBN.
“The main discovery in this work is that a monocrystal across a wafer can be achieved, and then they can move it,” Yakobson said. “Then they can make devices.”
“There is no existing method that can produce hBN monolayer dielectrics with extremely high reproducibility on a wafer, which is necessary for the electronics industry,” Li added. “This paper reveals the scientific reasons why we can achieve this.”
Yakobson hopes the technique may also apply broadly to other 2D materials, with some trial and error. “I think the underlying physics is pretty general,” he said. “Boron nitride is a big-deal material for dielectrics, but many desirable 2D materials, like the 50 or so transition metal dichalcogenides, have the same issues with growth and transfer, and may benefit from what we discovered.”
In 1975, Intel’s Gordon Moore predicted that the number of transistors in an integrated circuit would double every two years. But as integrated circuit architectures get smaller, with circuit lines down to a few nanometers, the pace of progress has been hard to maintain.
The ability to stack 2D layers, each with millions of transistors, may overcome such limitations if they can be isolated from one other. Insulating hBN is a prime candidate for that purpose because of its wide band gap.
Despite having “hexagonal” in its name, monolayers of hBN as seen from above appear as a superposition of two distinct triangular lattices of boron and nitrogen atoms. For the material to perform up to spec, hBN crystals must be perfect; that is, the triangles have to be connected and all point in the same direction. Non-perfect crystals have grain boundaries that degrade the material’s electronic properties.
For hBN to become perfect, its atoms have to precisely align with those on the substrate below. The researchers found that copper in a (111) arrangement — the number refers to how the crystal surface is oriented — does the job, but only after the copper is annealed at high temperature on a sapphire substrate and in the presence of hydrogen.
Annealing eliminates grain boundaries in the copper, leaving a single crystal. Such a perfect surface would, however, be “way too smooth” to enforce the hBN orientation, Yakobson said.
Yakobson reported on research last year to grow pristine borophene on silver (111), and also a theoretical prediction that copper can align hBN by virtue of the complementary steps on its surface. The copper surface was vicinal — that is, slightly miscut to expose atomic steps between the expansive terraces. That paper caught the attention of industrial researchers in Taiwan, who approached the professor after a talk there last year.
“They said, ‘We read your paper,’” Yakobson recalled. “‘We see something strange in our experiments. Can we talk?’ That’s how it started.”
Informed by his earlier experience, Yakobson suggested that thermal fluctuations allow copper (111) to retain step-like terraces across its surface, even when its own grain boundaries are eliminated. The atoms in these meandering “steps” present just the right interfacial energies to bind and constrain hBN, which then grows in one direction while it attaches to the copper plane via the very weak van der Waals force.
Researchers in Taiwan, China and at Rice made wafer-sized, two-dimensional sheets of hexagonal boron nitride, as reported in Nature. The material may be removed from its copper substrate and used as a dielectric for two-dimensional electronics.
“Every surface has steps, but in the prior work, the steps were on a hard-engineered vicinal surface, which means they all go down, or all up,” he said. “But on copper (111), the steps are up and down, by just an atom or two randomly, offered by the fundamental thermodynamics.”
Because of the copper’s orientation, the horizontal atomic planes are offset by a fraction to the lattice underneath. “The surface step-edges look the same, but they’re not exact mirror-twins,” Yakobson explained. “There’s a larger overlap with the layer below on one side than on the opposite.”
That makes the binding energies on each side of the copper plateau different by a minute 0.23 electron volts (per every quarter-nanometer of contact), which is enough to force docking hBN nuclei to grow in the same direction, he said.
The experimental team found the optimal copper thickness was 500 nanometers, enough to prevent its evaporation during hBN growth via chemical vapor deposition of ammonia borane on a copper (111)/sapphire substrate.
Tse-An Chen of TSMC is co-lead author of the paper. Co-authors are Chien-Chih Tseng, Chao-Kai Wen, Wei-Chen Chueh and Wen-Hao Chang of Chiao Tung; H.-S. Philip Wong and Tsu-Ang Chao of TSMC; Shuangyuan Pan and Yanfeng Zhang of Peking University, China; Qiang Fu of the Chinese Academy of Sciences, Dalian, China; and Rongtan Li of the Chinese Academy of Sciences and the University of Chinese Academy of Sciences, Beijing.
Yakobson is the Karl F. Hasselmann Professor of Materials Science and NanoEngineering and a professor of chemistry at Rice. Chang is a professor at Chiao Tung and director of the university’s Center for Emergent Functional Matter Science. Li is Director, Corporate Research, Taiwan Semiconductor Manufacturing Co.
The research was supported by TSMC, the Ministry of Science and Technology of Taiwan, the Ministry of Education of Taiwan, the National Natural Science Foundation of China, the Chinese Academy of Sciences and the U.S. Department of Energy.
A small step for atoms, a giant leap for microelectronics | Rice University
Nature paper reports making and moving large-scale hexagonal boron nitride
HOUSTON – (March 4, 2020) – Step by step, scientists are figuring out new ways to extend Moore’s Law. The latest reveals a path toward integrated circuits with two-dimensional transistors.
A Rice University scientist and his collaborators in Taiwan and China reported in Nature today that they have successfully grown atom-thick sheets of hexagonal boron nitride (hBN) as two-inch diameter crystals across a wafer.
Surprisingly, they achieved the long-sought goal of making perfectly ordered crystals of hBN, a wide band gap semiconductor, by taking advantage of disorder among the meandering steps on a copper substrate. The random steps keep the hBN in line.
Set into chips as a dielectric between layers of nanoscale transistors, wafer-scale hBN would excel in damping electron scattering and trapping that limit the efficiency of an integrated circuit. But until now, nobody has been able to make perfectly ordered hBN crystals that are large enough — in this case, on a wafer — to be useful.
Brown School of Engineering materials theorist Boris Yakobson is co-lead scientist on the study with Lain-Jong (Lance) Li of the Taiwan Semiconductor Manufacturing Co. (TSMC) and his team. Yakobson and Chih-Piao Chuu of TSMC performed theoretical analysis and first principles calculations to unravel the mechanisms of what their co-authors saw in experiments.
As a proof of concept for manufacturing, experimentalists at TSMC and Taiwan’s National Chiao Tung University grew a two-inch, 2D hBN film, transferred it to silicon and then placed a layer of field-effect transistors patterned onto 2D molybdenum disulfide atop the hBN.
“The main discovery in this work is that a monocrystal across a wafer can be achieved, and then they can move it,” Yakobson said. “Then they can make devices.”
“There is no existing method that can produce hBN monolayer dielectrics with extremely high reproducibility on a wafer, which is necessary for the electronics industry,” Li added. “This paper reveals the scientific reasons why we can achieve this.”
Yakobson hopes the technique may also apply broadly to other 2D materials, with some trial and error. “I think the underlying physics is pretty general,” he said. “Boron nitride is a big-deal material for dielectrics, but many desirable 2D materials, like the 50 or so transition metal dichalcogenides, have the same issues with growth and transfer, and may benefit from what we discovered.”
In 1975, Intel’s Gordon Moore predicted that the number of transistors in an integrated circuit would double every two years. But as integrated circuit architectures get smaller, with circuit lines down to a few nanometers, the pace of progress has been hard to maintain.
The ability to stack 2D layers, each with millions of transistors, may overcome such limitations if they can be isolated from one other. Insulating hBN is a prime candidate for that purpose because of its wide band gap.
Despite having “hexagonal” in its name, monolayers of hBN as seen from above appear as a superposition of two distinct triangular lattices of boron and nitrogen atoms. For the material to perform up to spec, hBN crystals must be perfect; that is, the triangles have to be connected and all point in the same direction. Non-perfect crystals have grain boundaries that degrade the material’s electronic properties.
For hBN to become perfect, its atoms have to precisely align with those on the substrate below. The researchers found that copper in a (111) arrangement — the number refers to how the crystal surface is oriented — does the job, but only after the copper is annealed at high temperature on a sapphire substrate and in the presence of hydrogen.
Annealing eliminates grain boundaries in the copper, leaving a single crystal. Such a perfect surface would, however, be “way too smooth” to enforce the hBN orientation, Yakobson said.
Yakobson reported on research last year to grow pristine borophene on silver (111), and also a theoretical prediction that copper can align hBN by virtue of the complementary steps on its surface. The copper surface was vicinal — that is, slightly miscut to expose atomic steps between the expansive terraces. That paper caught the attention of industrial researchers in Taiwan, who approached the professor after a talk there last year.
“They said, ‘We read your paper,’” Yakobson recalled. “‘We see something strange in our experiments. Can we talk?’ That’s how it started.”
Informed by his earlier experience, Yakobson suggested that thermal fluctuations allow copper (111) to retain step-like terraces across its surface, even when its own grain boundaries are eliminated. The atoms in these meandering “steps” present just the right interfacial energies to bind and constrain hBN, which then grows in one direction while it attaches to the copper plane via the very weak van der Waals force.
“Every surface has steps, but in the prior work, the steps were on a hard-engineered vicinal surface, which means they all go down, or all up,” he said. “But on copper (111), the steps are up and down, by just an atom or two randomly, offered by the fundamental thermodynamics.”
Because of the copper’s orientation, the horizontal atomic planes are offset by a fraction to the lattice underneath. “The surface step-edges look the same, but they’re not exact mirror-twins,” Yakobson explained. “There’s a larger overlap with the layer below on one side than on the opposite.”
That makes the binding energies on each side of the copper plateau different by a minute 0.23 electron volts (per every quarter-nanometer of contact), which is enough to force docking hBN nuclei to grow in the same direction, he said.
The experimental team found the optimal copper thickness was 500 nanometers, enough to prevent its evaporation during hBN growth via chemical vapor deposition of ammonia borane on a copper (111)/sapphire substrate.
Tse-An Chen of TSMC is co-lead author of the paper. Co-authors are Chien-Chih Tseng, Chao-Kai Wen, Wei-Chen Chueh and Wen-Hao Chang of Chiao Tung; H.-S. Philip Wong and Tsu-Ang Chao of TSMC; Shuangyuan Pan and Yanfeng Zhang of Peking University, China; Qiang Fu of the Chinese Academy of Sciences, Dalian, China; and Rongtan Li of the Chinese Academy of Sciences and the University of Chinese Academy of Sciences, Beijing.
Yakobson is the Karl F. Hasselmann Professor of Materials Science and NanoEngineering and a professor of chemistry at Rice. Chang is a professor at Chiao Tung and director of the university’s Center for Emergent Functional Matter Science. Li is Director, Corporate Research, Taiwan Semiconductor Manufacturing Co.
The research was supported by TSMC, the Ministry of Science and Technology of Taiwan, the Ministry of Education of Taiwan, the National Natural Science Foundation of China, the Chinese Academy of Sciences and the U.S. Department of Energy.
A small step for atoms, a giant leap for microelectronics | Rice University
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UNISOC Unveils T7520 SoC for 5G Smartphones: Octa-Core, 6nm EUV
by Anton Shilov on March 4, 2020 10:00 AM EST
UNISOC, formerly Spreadtrum Semiconductor, has announced its first mobile application processor with an integrated 5G modem. Dubbed the T7520, the SoC also happens to be one of the world’s first chips to be made using TSMC’s 6 nm process technology, which uses extreme ultraviolet lithography (EUVL) for several layers.
The UNISOC T7520 application processor packs four high-performance Arm Cortex-A76 cores, four energy-efficient Arm Cortex-A55 cores, as well as an Arm Mali-G57 GPU with a display engine that supports multiple screens with a 4K resolution and HDR10+. Furthermore, the SoC integrates a new NPU that is said to offer a 50% higher TOPS-per-Watt rate than the company’s previous-generation NPU. In addition, the chip features a four-core ISP that supports up to 100 MP sensors and multi-camera processing capability. Finally, the AP also features the company’s latest Secure Element processor that supports ‘most of crypto algorithms’ and can handle compute-intensive security scenarios, such as encrypted video calls.
One of the key features of the UNISOC T7520 is of course its integrated 2G/3G/4G/5G-supporting modem, which supports 5G NR TDD+FDD carrier aggregation, as well as uplink and downlink decoupling for enhanced coverage. All told, the T7520's modem is designed to offer peak uplink speed of 3.25 Gbps.
The high level of integration of the T7520 SoC is designed to enable smartphone manufacturers to build more reasonably priced 5G handsets, which will inevitably increase their popularity and adoption of the technology. Meanwhile, usage of TSMC’s 6 nm fabrication technology (known as N6) should allow UNISOC to make the AP for less than compared to non-EUV fabrication processes.
UNISOC did not announce when it plans to start shipments of its T7520 application processor, though it is reasonable to expect it to become available this year.
https://www.anandtech.com/show/15576/unisoc-unveils-t7520-soc-for-5g-smartphones-octacore-6nm-euv
Bad news for Qualcomm.
by Anton Shilov on March 4, 2020 10:00 AM EST
UNISOC, formerly Spreadtrum Semiconductor, has announced its first mobile application processor with an integrated 5G modem. Dubbed the T7520, the SoC also happens to be one of the world’s first chips to be made using TSMC’s 6 nm process technology, which uses extreme ultraviolet lithography (EUVL) for several layers.
The UNISOC T7520 application processor packs four high-performance Arm Cortex-A76 cores, four energy-efficient Arm Cortex-A55 cores, as well as an Arm Mali-G57 GPU with a display engine that supports multiple screens with a 4K resolution and HDR10+. Furthermore, the SoC integrates a new NPU that is said to offer a 50% higher TOPS-per-Watt rate than the company’s previous-generation NPU. In addition, the chip features a four-core ISP that supports up to 100 MP sensors and multi-camera processing capability. Finally, the AP also features the company’s latest Secure Element processor that supports ‘most of crypto algorithms’ and can handle compute-intensive security scenarios, such as encrypted video calls.
One of the key features of the UNISOC T7520 is of course its integrated 2G/3G/4G/5G-supporting modem, which supports 5G NR TDD+FDD carrier aggregation, as well as uplink and downlink decoupling for enhanced coverage. All told, the T7520's modem is designed to offer peak uplink speed of 3.25 Gbps.
The high level of integration of the T7520 SoC is designed to enable smartphone manufacturers to build more reasonably priced 5G handsets, which will inevitably increase their popularity and adoption of the technology. Meanwhile, usage of TSMC’s 6 nm fabrication technology (known as N6) should allow UNISOC to make the AP for less than compared to non-EUV fabrication processes.
UNISOC did not announce when it plans to start shipments of its T7520 application processor, though it is reasonable to expect it to become available this year.
https://www.anandtech.com/show/15576/unisoc-unveils-t7520-soc-for-5g-smartphones-octacore-6nm-euv
Bad news for Qualcomm.
antonius123
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SMIC 7nm process to be introduced in Q4 with 20% performance improvement
February 27, 2020
0 1
The 7nm process of Semiconductor Manufacturing International Corporation (SMIC), China's most advanced and largest foundry, will begin small-scale production in the fourth quarter, according to kkj.cn.
Compared with 14nm, SMIC's N+1 process improves performance by 20%, reduces power consumption by 57%, reduces logic area by 63%, and reduces SoC area by 55%, the report cited Dr. Liang Mengsong, co-CEO of SMIC, as saying.
TSMC and Samsung will mass produce 5nm processes this year, and China's advanced processes are still catching up.
The largest wafer foundry, SMIC, mass-produced a 14nm process at the end of last year, which brought 1% of revenue and revenue of $7.69 million, but this process technology can already meet 95% of domestic demand.
The 14nm and improved 12nm processes are SMIC's first-generation FinFET processes. They are also developing more advanced N+1 including N+2 FinFET processes, which are equivalent to low-power, high-performance versions of the 7nm process.
After N+1, there will also be N+2. These two processes perform similarly in terms of power consumption. The difference lies in performance and cost. N+2 is obviously oriented towards high performance and the cost will increase.
As for the EUV lithography machine that has attracted much attention, Liang Mengsong said that under the current environment, N+1 and N+2 generation processes will not use the EUV process. After the equipment is ready, the N+2 process may have several photomasks. With EUV, the subsequent process will switch to EUV lithography on a large scale.
Now the most important thing is when SMIC will be mass-produced at 7nm. The latest news says that SMIC's N+1 FinFET process has been introduced by customers (but no customer list has been announced). Small-scale production will begin in the fourth quarter of this year, earlier than previously reported.
In order to accelerate advanced process capacity, SMIC's capital expenditure will reach US $ 3.1 billion this year (the company's annual revenue is only around US $3 billion), of which US $2 billion will be used for SMIC's 12-inch wafer fab in Shanghai and US $500 million At a 12-inch wafer fab in Beijing.
https://cntechpost.com/2020/02/27/smic-7nm-process-to-be-introduced-in-q4/
February 27, 2020
0 1
The 7nm process of Semiconductor Manufacturing International Corporation (SMIC), China's most advanced and largest foundry, will begin small-scale production in the fourth quarter, according to kkj.cn.
Compared with 14nm, SMIC's N+1 process improves performance by 20%, reduces power consumption by 57%, reduces logic area by 63%, and reduces SoC area by 55%, the report cited Dr. Liang Mengsong, co-CEO of SMIC, as saying.
TSMC and Samsung will mass produce 5nm processes this year, and China's advanced processes are still catching up.
The largest wafer foundry, SMIC, mass-produced a 14nm process at the end of last year, which brought 1% of revenue and revenue of $7.69 million, but this process technology can already meet 95% of domestic demand.
The 14nm and improved 12nm processes are SMIC's first-generation FinFET processes. They are also developing more advanced N+1 including N+2 FinFET processes, which are equivalent to low-power, high-performance versions of the 7nm process.
After N+1, there will also be N+2. These two processes perform similarly in terms of power consumption. The difference lies in performance and cost. N+2 is obviously oriented towards high performance and the cost will increase.
As for the EUV lithography machine that has attracted much attention, Liang Mengsong said that under the current environment, N+1 and N+2 generation processes will not use the EUV process. After the equipment is ready, the N+2 process may have several photomasks. With EUV, the subsequent process will switch to EUV lithography on a large scale.
Now the most important thing is when SMIC will be mass-produced at 7nm. The latest news says that SMIC's N+1 FinFET process has been introduced by customers (but no customer list has been announced). Small-scale production will begin in the fourth quarter of this year, earlier than previously reported.
In order to accelerate advanced process capacity, SMIC's capital expenditure will reach US $ 3.1 billion this year (the company's annual revenue is only around US $3 billion), of which US $2 billion will be used for SMIC's 12-inch wafer fab in Shanghai and US $500 million At a 12-inch wafer fab in Beijing.
https://cntechpost.com/2020/02/27/smic-7nm-process-to-be-introduced-in-q4/
Beidou2020
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Chinese researchers develop high-performance integrated solid-state quantum memory
Xinhua
Updated: March 11, 2020
[Photo/ustc.edu.cn]
HEFEI -- Chinese researchers have developed a high-fidelity integrated solid-state quantum memory, making important progress in the field of quantum storage and laying a solid foundation for developing a quantum network.
The achievement was made by a team of researchers led by Li Chuanfeng and Zhou Zongquan with the University of Science and Technology of China. It has been published in the journals Optica and Applied Physics Reviews.
As a core device for constructing a quantum network, quantum memory can effectively overcome channel loss, expand the distance of quantum communication, and integrate quantum computing and quantum sensing resources in different locations.
The integrated solid-state quantum memory was developed by using femtosecond laser micro-machining technology, which for the first time, etched optical waveguides in yttrium silicate crystals, according to the researchers.
They also demonstrated two kinds of optical quantum storage schemes, which achieved a fidelity rate of over 99 percent and 97 percent, respectively.
Reviewers of Optica said the study was important because it demonstrated the diversity of experimental techniques and schemes.
The study proved that etched waveguides in rare-earth-doped crystals are a promising platform in the field of quantum information, according to the reviewers.
Xinhua
Updated: March 11, 2020
[Photo/ustc.edu.cn]
HEFEI -- Chinese researchers have developed a high-fidelity integrated solid-state quantum memory, making important progress in the field of quantum storage and laying a solid foundation for developing a quantum network.
The achievement was made by a team of researchers led by Li Chuanfeng and Zhou Zongquan with the University of Science and Technology of China. It has been published in the journals Optica and Applied Physics Reviews.
As a core device for constructing a quantum network, quantum memory can effectively overcome channel loss, expand the distance of quantum communication, and integrate quantum computing and quantum sensing resources in different locations.
The integrated solid-state quantum memory was developed by using femtosecond laser micro-machining technology, which for the first time, etched optical waveguides in yttrium silicate crystals, according to the researchers.
They also demonstrated two kinds of optical quantum storage schemes, which achieved a fidelity rate of over 99 percent and 97 percent, respectively.
Reviewers of Optica said the study was important because it demonstrated the diversity of experimental techniques and schemes.
The study proved that etched waveguides in rare-earth-doped crystals are a promising platform in the field of quantum information, according to the reviewers.
Beidou2020
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Chinese startup Cambricon Technologies challenges Nvidia’s dominance in AI chip market
©Cambricon Technologies
This ambitious AI chip maker takes aim at the future with a series of world-class products
US technology company Nvidia, valued at over US$100 billion, currently enjoys a formidable lead in the global AI chip race. But a rising Chinese startup, Cambricon Technologies, is hot on its tail.
Cambricon Technologies co-founder Chen Yunji has said that the company aims to improve AI chip computing efficiency by 10,000 times and reduce chip power consumption 10,000-fold. Founder and CEO Chen Tianshi said in a speech that the company would corner 30% of China’s high-performance AI chip market and embed one billion devices worldwide with its chips within three years. The seemingly wild talk, backed up by the startup team’s impressive technological prowess and generous financing from investors like Alibaba, isn’t just castles in the sky.
Aim higher
Cambricon Technologies is backed by the Chinese Academy of Sciences (CAS), one of China's most prestigious scientific research institutions. Talented brothers and co-founders Chen Tianshi and Chen Yunji are professors at CAS and experts in processor architecture and AI. All of Cambricon’s key team members have over eight years of experience in chip design and AI research and are graduates of China’s top research universities.
Proof that the company is not all talk, Cambricon Technologies has created a line of groundbreaking AI chips. In May 2018, Cambricon released its new MLU100 model. The AI chip supports cloud-based machine learning, including vision, audio and natural language processing under complex scenarios. The MLU100 makes Cambricon the first company in China - and one of only a few companies in the world - that owns intellectual property that supports both cloud and edge computing.
The startup also unveiled the Cambricon-1M, a third-generation edge-based AI chip with a reported efficiency of 5 TOPS/Watt for 8-bit computing, making it the world’s first smart product that enables local machine training. Users can provide voice and vision inputs to any device locally without needing cloud connectivity, thus relieving many concerns about user privacy.
Before the release of the 1M, one of Cambricon’s most profitable products was the Cambricon-1A, the first deep learning processing chip successfully put into commercial use. Huawei, the third largest smartphone maker in the world, chose the 1A to develop the Kirin 970 chip that powers its flagship Mate 10 models.
Think bigger
In addition to pursuing AI chip sovereignty, Cambricon also wants to make the latest technological developments available to everyone. To achieve this goal, Cambricon chose not to use general-purpose Graphic Processing Units (GPUs) like Nvidia. Instead, Cambricon employs Neural Processing Units (NPUs) to handle AI workloads and customizes Application-Specific Integrated Circuits (ASICs) for specific uses. The cost of the traditional GPU/CPU-powered chip is prohibitive for everyday use. The electricity needed to run a GPU/CPU-powered chip for a minute costs US$300, giving users enough time to play one very expensive game of online chess. The average power consumption of NPUs and ASICs is around one-tenth of mainstream CPUs and their average performance level is 100 times that of GPUs.
Cambricon’s new products have been well received by several of its partners already, including Lenovo Group, Sugon Information Industry Co., Ltd. and iFlytek, all three of which have launched systems or products carrying Cambricon’s latest chips.
We are likely about to witness an AI explosion. Those who have prepared ahead of time stand to gain a great deal. Cambricon has been waiting for the bomb to go off for some time now. Are you ready?
- Dec 03, 2018
- By Irene Wang
©Cambricon Technologies
This ambitious AI chip maker takes aim at the future with a series of world-class products
US technology company Nvidia, valued at over US$100 billion, currently enjoys a formidable lead in the global AI chip race. But a rising Chinese startup, Cambricon Technologies, is hot on its tail.
Cambricon Technologies co-founder Chen Yunji has said that the company aims to improve AI chip computing efficiency by 10,000 times and reduce chip power consumption 10,000-fold. Founder and CEO Chen Tianshi said in a speech that the company would corner 30% of China’s high-performance AI chip market and embed one billion devices worldwide with its chips within three years. The seemingly wild talk, backed up by the startup team’s impressive technological prowess and generous financing from investors like Alibaba, isn’t just castles in the sky.
Aim higher
Cambricon Technologies is backed by the Chinese Academy of Sciences (CAS), one of China's most prestigious scientific research institutions. Talented brothers and co-founders Chen Tianshi and Chen Yunji are professors at CAS and experts in processor architecture and AI. All of Cambricon’s key team members have over eight years of experience in chip design and AI research and are graduates of China’s top research universities.
Proof that the company is not all talk, Cambricon Technologies has created a line of groundbreaking AI chips. In May 2018, Cambricon released its new MLU100 model. The AI chip supports cloud-based machine learning, including vision, audio and natural language processing under complex scenarios. The MLU100 makes Cambricon the first company in China - and one of only a few companies in the world - that owns intellectual property that supports both cloud and edge computing.
The startup also unveiled the Cambricon-1M, a third-generation edge-based AI chip with a reported efficiency of 5 TOPS/Watt for 8-bit computing, making it the world’s first smart product that enables local machine training. Users can provide voice and vision inputs to any device locally without needing cloud connectivity, thus relieving many concerns about user privacy.
Before the release of the 1M, one of Cambricon’s most profitable products was the Cambricon-1A, the first deep learning processing chip successfully put into commercial use. Huawei, the third largest smartphone maker in the world, chose the 1A to develop the Kirin 970 chip that powers its flagship Mate 10 models.
Think bigger
In addition to pursuing AI chip sovereignty, Cambricon also wants to make the latest technological developments available to everyone. To achieve this goal, Cambricon chose not to use general-purpose Graphic Processing Units (GPUs) like Nvidia. Instead, Cambricon employs Neural Processing Units (NPUs) to handle AI workloads and customizes Application-Specific Integrated Circuits (ASICs) for specific uses. The cost of the traditional GPU/CPU-powered chip is prohibitive for everyday use. The electricity needed to run a GPU/CPU-powered chip for a minute costs US$300, giving users enough time to play one very expensive game of online chess. The average power consumption of NPUs and ASICs is around one-tenth of mainstream CPUs and their average performance level is 100 times that of GPUs.
Cambricon’s new products have been well received by several of its partners already, including Lenovo Group, Sugon Information Industry Co., Ltd. and iFlytek, all three of which have launched systems or products carrying Cambricon’s latest chips.
We are likely about to witness an AI explosion. Those who have prepared ahead of time stand to gain a great deal. Cambricon has been waiting for the bomb to go off for some time now. Are you ready?
Beidou2020
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Alibaba develops its first AI and IoT chip, based on RISC-V architecture
Helping decrease China's dependence on foreign-designed chips
July 26, 2019
By Will Calvert
Alibaba subsidiary Pintouge has developed its first chip based on an open source architecture.
While plans for the chips were announced before recent trade tensions with the US escalated, the Xuantie 910 processor comes after Washington blacklisted several Chinese tech firms, cutting Huawei off from the Arm architecture.
Pintouge's first product, Xuantie is intended for IoT, 5G and AI applications.
– Alibaba
Self-sufficiency
Based on RISC-V, an open source chip architecture, the processor could offer an alternative to the Arm architecture, which many Chinese companies rely on. As it is open source, RISC-V cannot be impacted by trade sanctions.
Alibaba will license the full IP to chip makers, opening a new revenue stream for the company. It also said it will release parts of related code for the product on GitHub to help expand the reach of the architecture.
“This new RISC-V processor is designed to serve a lot more heavy-duty IoT applications that require high-performance computing, such as AI, networking, gateway, self-driving automobile and edge servers,” Alibaba said in a statement.
“We believe the new processor would also help drive the growth of the RISC-V open-source community in Asia and globally.”
Chinese tech companies are keen to shift away from their dependence on foreign semiconductor manufacturers amid US sanctions. Bloomberg reports that China imports roughly three times as many chips as it produces and spends more on semiconductors than it does on oil.
There are currently two Chinese industry organizations dedicated to promoting RISC-V, The China Open Instruction Eco System Alliance (CRVA) and China RISC-V Industry Consortium (CRVIC).
The US simply has one such group, the RISC-V Foundation. CRVA seems more interested in open-source aspects of RISC-V while CRVIC is focused on commercializing the chips.
Helping decrease China's dependence on foreign-designed chips
July 26, 2019
By Will Calvert
Alibaba subsidiary Pintouge has developed its first chip based on an open source architecture.
While plans for the chips were announced before recent trade tensions with the US escalated, the Xuantie 910 processor comes after Washington blacklisted several Chinese tech firms, cutting Huawei off from the Arm architecture.
Pintouge's first product, Xuantie is intended for IoT, 5G and AI applications.
– Alibaba
Self-sufficiency
Based on RISC-V, an open source chip architecture, the processor could offer an alternative to the Arm architecture, which many Chinese companies rely on. As it is open source, RISC-V cannot be impacted by trade sanctions.
Alibaba will license the full IP to chip makers, opening a new revenue stream for the company. It also said it will release parts of related code for the product on GitHub to help expand the reach of the architecture.
“This new RISC-V processor is designed to serve a lot more heavy-duty IoT applications that require high-performance computing, such as AI, networking, gateway, self-driving automobile and edge servers,” Alibaba said in a statement.
“We believe the new processor would also help drive the growth of the RISC-V open-source community in Asia and globally.”
Chinese tech companies are keen to shift away from their dependence on foreign semiconductor manufacturers amid US sanctions. Bloomberg reports that China imports roughly three times as many chips as it produces and spends more on semiconductors than it does on oil.
There are currently two Chinese industry organizations dedicated to promoting RISC-V, The China Open Instruction Eco System Alliance (CRVA) and China RISC-V Industry Consortium (CRVIC).
The US simply has one such group, the RISC-V Foundation. CRVA seems more interested in open-source aspects of RISC-V while CRVIC is focused on commercializing the chips.
Beidou2020
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Chinese Fab SMIC to Start 7nm Production in the Fourth Quarter: Report
By Arne Verheyde
First Published 4 weeks ago
SMIC is investing to accelerate its advanced processes.
(Image credit: Shutterstock)
Semiconductor Manufacturing International Corporation (SMIC), China's largest foundry, has scheduled initial 7nm production for the fourth quarter of this year, according to kkj.cn and reported by CNTechPost. Density is more than doubled compared to 14nm, which started production late last year.
Dr. Liang Mengsong, co-CEO of SMIC, reportedly said that 7nm, as successor to its 14nm process, improves performance by 20% and reduces power consumption by 57%. It would reduce logic area by 63% and reduce SoC area by 55%, which suggests that density is more than twice that of its 14nm.
SMIC started 14nm production in late 2019, which is its first-generation FinFET process technology, according to CNTechPost, so this would imply that 7nm is following closely with (small-scale) production in the fourth quarter. This would be earlier than previously expected. SMIC is also developing a second, high-performance variant of its 7nm (N+1), called N+2. Both variants don’t use EUV.
To support its advanced process capacity, SMIC's capital spending is expected to reach $3.1 billion this year, compared to annual revenue of only around $3 billion.
As a trailing edge foundry, SMIC would still be behind leading foundry TSMC by almost three years, but this can be considered fairly respectable given the large costs involved with leading edge process nodes. TSMC started 7nm volume production in the first half of 2018 and will start production of 5nm in the first half of this year.
By Arne Verheyde
First Published 4 weeks ago
SMIC is investing to accelerate its advanced processes.
(Image credit: Shutterstock)
Semiconductor Manufacturing International Corporation (SMIC), China's largest foundry, has scheduled initial 7nm production for the fourth quarter of this year, according to kkj.cn and reported by CNTechPost. Density is more than doubled compared to 14nm, which started production late last year.
Dr. Liang Mengsong, co-CEO of SMIC, reportedly said that 7nm, as successor to its 14nm process, improves performance by 20% and reduces power consumption by 57%. It would reduce logic area by 63% and reduce SoC area by 55%, which suggests that density is more than twice that of its 14nm.
SMIC started 14nm production in late 2019, which is its first-generation FinFET process technology, according to CNTechPost, so this would imply that 7nm is following closely with (small-scale) production in the fourth quarter. This would be earlier than previously expected. SMIC is also developing a second, high-performance variant of its 7nm (N+1), called N+2. Both variants don’t use EUV.
To support its advanced process capacity, SMIC's capital spending is expected to reach $3.1 billion this year, compared to annual revenue of only around $3 billion.
As a trailing edge foundry, SMIC would still be behind leading foundry TSMC by almost three years, but this can be considered fairly respectable given the large costs involved with leading edge process nodes. TSMC started 7nm volume production in the first half of 2018 and will start production of 5nm in the first half of this year.
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