Yangtze Memory Technologies Introduces New 3D NAND Architecture -- XtackingTM
Date: 2018-08-06
Wuhan, China, August 6, 2018 - Yangtze Memory Technologies Co., Ltd (YMTC), a new player in the NAND industry, today announced its ground-breaking technology -
XtackingTM, which will provide unprecedented NAND I/O performance, higher bit density and faster time-to-market.
With
XtackingTM, the periphery circuits which handle data I/O as well as memory cell operations are processed on a separate wafer using the logic technology node that enables the desired I/O speed and functions. Once the processing of the array wafer is completed, the two wafers are connected electrically through millions of metal VIAs (Vertical Interconnect Accesses) that are formed simultaneously across the whole wafer in one process step, using the innovative XtackingTM technology, with limited increase in total cost.
“As monolithic die density increases with each successive generation of 3D NAND, it becomes much more challenging to maintain or improve performance for a given SSD capacity. Higher I/O speed and multi-plane operation will be necessary to achieve the required SSD performance going forward,” said
Gregory Wong, Founder and Principal Analyst at Forward Insights, a renowned market intelligence firm in the field of NAND flash memories and solid-state storage.
“At present, the world’s highest 3D NAND I/O speed is targeting 1.4Gbps while the majority of the industry is offering NAND I/O at 1.0Gbps or below. With our XtackingTM technology, it is possible for NAND I/O speed to reach up to 3.0Gpbs, similar to I/O speed of DRAM DDR4. This is going to be a game changer in the NAND industry,” said
Simon Yang, CEO at YMTC.
In the conventional 3D NAND architecture, the periphery circuits take up ~20-30% of the die area, lowering NAND bit density. As 3D NAND technology continues to progress to 128 layers and above, the periphery circuits will likely take up more than 50% of the total die area. With XtackingTM, the periphery circuits are now above the array chip, enabling much higher NAND bit density than conventional 3D NAND.
XtackingTM technology utilizes fully independent processing of the array and periphery, which offers a modularized, parallel approach to product development and manufacturing, reducing product development time by at least three months and shortening manufacturing cycle time by 20%, significantly accelerating 3D NAND time-to-market. This modular approach also opens possibilities for customized NAND flash solutions by the incorporation of innovative functionalities in the periphery.
YMTC has successfully utilized this innovative XtackingTM technology in its 2nd generation 3D NAND development, targeting to go to mass production in 2019. With help from customers, industry partners and standard bodies, XtackingTM ushers in a brand-new chapter in high-performance customized NAND solutions for smartphone, personal computing, data center and enterprise applications.
Yangtze Memory Technologies Introduces New 3D NAND Architecture -- XtackingTM｜YMTC
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News & Analysis
YMTC Adds Detail to NAND Plans
Xtacking chips run up to 3.0 Gbits/second
Rick Merritt
8/6/2018 09:00 AM EDT SANTA CLARA, Calif. — Yangtze Memory Technologies Co. (YMTC) revealed more details about its 3D NAND plans ahead of a talk on Tuesday at the
Flash Memory Summit. The company aims to deliver 256-Gbit chips late next year supporting data rates up to 3.0 Gbits/s, more than twice as fast as the competition.
YMTC’s talk will mark the first public discussion of an effort from China to produce leading-edge memory chips. Analysts were skeptical of the new product’s impact given that it will be behind rivals in density and the company has yet to prove that the chips can reach commercial yields.
Plans for the 64-layer, 3-bit-per-cell chips emerge at a time when rivals Intel, Micron, Samsung, and Toshiba/WD have announced or are shipping 96-layer, 4-bit-per-cell devices delivering 256 Gbits and above. Samsung said that its chips will support data rates up to 1.4 Gbits/s while others are expected to run at 1.0 Gbits/s.
The so-called Xstacking approach at YMTC aims to increase bit density by making NAND and I/O arrays on separate die. The chips are bonded with millions of what YMTC describes as metal vertical interconnect accesses created in a single process step.
YMTC claims that its approach significantly increases NAND bit density and helps it achieve as good or better cost per bit as competitors. The technique also shortens product development time by at least three months and manufacturing cycle time by 20%, said the company. In addition, it opens a door to customizing chips by adding unique logic functions to the I/O die, initially made in a 180-nm process.
“This is going to be a game changer in the NAND industry,” said Simon Yang, chief executive of YMTC, in a press statement.
The chips will work with multiple flash controllers, said the company, but it did not provide names of any partners. Meanwhile, it plans to be in volume production of conventional 32-layer NAND chips by October, and it has a second-generation Xstacking product in development.
YMTC has been working for years on its flash chips and its 32L plans are on track with its stated roadmap,” said Alan Niebel, memory analyst at Web-Feet Research. However, “it has a difficult challenge to bring yields up, actually manufacture parts, and still catch up with the incumbents that are three generations ahead.”
“I am not sure whether the market will adopt something that has a high-speed interface in front of a slow memory technology — NAND flash is really slow,” said Jim Handy, memory analyst at Objective Analysis. “I would guess that ONFi and Toggle Mode would perform about as well.”
“PMC Sierra and Toshiba showed off something similar [to Xstacking] a few years ago at the Flash Memory Summit,” he added. “It used a very high-speed PMC logic chip under a stack of NAND chips that connected through TSVs. YMTC’s approach is a little different because it doesn’t use the costly TSVs in exchange for being able to stack only a single NAND chip above the logic chip.”
Without a new approach, I/O circuits will rise from taking up 20% to 30% of a 3D NAND die today to more than 50% for chips with 128 layers and beyond, said YMTC.
“As monolithic die density increases with each successive generation of 3D NAND, it becomes much more challenging to maintain or improve performance for a given [sold-state drive] capacity,” said Gregory Wong, principal analyst at Forward Insights, quoted in YMTC’s press statement. “Higher I/O speed and multi-plane operation will be necessary to achieve the required SSD performance going forward.”
The company, described as the pride of China, has long been seen as one of the country’s most likely candidates to deliver a commercially viable mainstream memory chip. It was founded in 2016 with a whopping $24 billion in funding, leveraging the 12-inch fabs of China’s XMC in Wuhan.
The YMTC news comes at a time of heightened trade tensions between the U.S. and China, where semiconductors have been a particular flash point.
Industry trade groups have long lobbied the U.S. government to help set a level playing field in China. The China government is
investing heavily in chips and requiring foreign firms to transfer their technology in exchange for market access, they claim. However,
they protested the Trump administration’s recent tariffs as an ineffective and even harmful approach.
In an
announcement last week, YMTC said that its Xtacking chips will be used in UFS as well as client and enterprise solid-state drives for use in smartphones, PCs, and data centers. The company will target global customers with the 48-layer chips, it said in an email exchange.
Ironically, Samsung, which was the first company to announce commercial 3D NAND chips at the Flash Memory Summit, is not participating in the event this year. The gap leaves YMTC an opening to be the talk of the show, at which all of the other major flash vendors are participating.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times
YMTC Adds Detail to NAND Plans | EE Times
