fudan university new 16-core cpu with message passing and shared-memory inter-core
27 February 2012, 10:06
Intel releases the instruction extension for transactional memory and gives numerous speeches at the International Solid-State Circuits Conference (ISSCC). AMD equips the Piledriver with inductors and China delivers another new processor.
While Intel and AMD explained some of the circuitry tricks of future processors, Oracle used the event to release more details about its already-launched SPARC T4 processor. The T4 comes with fewer but much more powerful cores than its T3 predecessor. It would be nice to have some benchmark results from SPECrate2006 to be able to directly compare the new 8-core chip with its 16-core predecessor, but apparently Oracle isn't willing to release them.
There were new processors to be admired, too, with a Chinese University yet again managing the feat of pulling a new one out of the hat. Last autumn, the Jiangnan Computing Research Lab delivered the ShenWei 1600 with 16 cores, which allowed an accordingly equipped computer to score 14th place in the Top500 supercomputer list. Now, the Fudan University from Shanghai has presented another interesting 16-core chip, which comes without caches and works with message passing as a cluster as well as with shared memory. The 16 SIMD RISC cores supposedly MIPS32 compatible are grouped in two clusters of 8 cores around a shared-memory node. The two clusters on a chip communicate with each other through three links. The processor, manufactured by TSMC in the 65nm process, manages a 3780 point FFT with 7MSamples/s. Clocked at 750MHz and with a voltage of 1.2 volts, it's supposed to have an operational power consumption of only 34mW/core. And so the Chinese have a head start here. It is just as well that at least ARM comes from Europe...
*ttp://www.h-online.com/newsticker/news/item/Processor-Whispers-About-elisions-and-epentheses-1442947.html