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IMECAS Developed High Performance Negative Capacitance FinFETs Featuring with both Ultra-Steep Subthreshold Swing and Enhanced Driving Current
Author: CUI Dongmeng
Update time: 2019-05-17
With the aggressive downscaling of Complementary Metal-Oxide-Semiconductor (CMOS) technology into sub-5 nm nodes, Si-based Field Effect Transistor, the key block of modern Integrated Circuit (IC), is confronted with a serious challenge i.e. tremendously increasing power consumption in a chip consisting of billons of transistors. Transistors of novel architectures, such as multi-gate (e.g. FinFET) or gate-all-around (GAA) devices with high-k/metal gate (HKMG), are able to work properly at small supply voltage with lowered power consumption. Nevertheless, a physical limit of Boltzmann tyranny originating from basic thermodynamics theory renders the subthreshold swing (SS) of a Si-based transistor no less than 60 mV/dec at room temperature, which unfortunately leads to the reluctant reduction of power consumption in state-of-the-art transistors.
By integrating hafnium based ferroelectric materials in the HKMG process, so-called differential negative capacitances (NC) can be realized under certain conditions to amplify the surface potential of the channel, thus breaking through the traditional Boltzmann tyranny and obtaining a steeper SS for significantly improved switching behavior. Consequently, a smaller supply voltage can be employed for the operation of IC. It is worth noting that even some progress has been made in recent years, the exploration of novel ferroelectric materials in mainstream FinFETs is, however, still in the inception phase and as-fabricated devices generally show poor performance due to numerous challenges of materials and integration process.
In order to cope with these challenges and accomplish the goal of reduced power consumption and improved device performance simultaneously, researchers from Integrated Circuit Advanced Process Center (ICAC) of Institute of Microelectronics, Chinese Academy of Sciences (IMECAS) have developed new processes for the growth of ferroelectric Hafnium Zirconium Oxide (HZO) and integration in FinFETs etc. High performance NC p-FinFETs of different gate lengths featuring with an ultra-thin 3-nm-thick ferroelectric HZO are demonstrated.
In detail, in order to realize a low interface defect density of HZO/SiO2/Si, both the atomic-layer deposition (ALD) process and post-annealing process have been carefully modulated during the growth of ultra-thin HZO. Thanks to the fully depleted Fin channels under strong 3D gate control, low interface defect density of HZO/SiO2/Si and appropriate engineering of capacitance matching, as-fabricated FinFETs show greatly improved subthreshold swing (SS) values i.e. 34.5 mV/dec with 500 nm gate length (LG) and 53 mV/dec with 20 nm LG, and small hysteresis voltages i.e. ~9 mV with 500 nm LG and ~40 mV with 20 nm LG. The SS is much smaller than Boltzmann tyranny of 60 mV/dec and the hysteresis voltage is well controlled to an acceptable level. In addition, compared to that of conventional FinFETs with general HfO2, a prominent enhancement of driving current by 260% is also obtained for as-fabricated NC FinFETs. The ratio between Ion and Ioff is as high as 1.23×106. Taking ultra-steep SS, enhanced driving current and small hysteresis into account, as-fabricated NC FinFETs in this work pave a way for developing core transistors with almost identical performance while remarkably lowered power consumption in the future. The latest results have been published in a prestigious journal “IEEE Electron Device Letters” (DOI: 10.1109/LED.2019.2891364).
This work was financially supported by the National Science and Technology Major Project 02 and the National Key Research and Development Program.
Fig. 1 (a) 3D schematic of NC FinFETs; (b-c) TEM images of NC p-FinFETs across AA’ directions; (d) Measured IDS-VGS curves of NC p-FinFET, where steep average SSfor and SSrev of 43.2 and 34.5 mV/decade are achieved,(e) extracted SS as a function of the IDS of the device in (d); (f) comparison between our work and reported NC FETs from other groups.
IMECAS Developed High Performance Negative Capacitance FinFETs Featuring with both Ultra-Steep Subthreshold Swing and Enhanced Driving Current
Author: CUI Dongmeng
Update time: 2019-05-17
With the aggressive downscaling of Complementary Metal-Oxide-Semiconductor (CMOS) technology into sub-5 nm nodes, Si-based Field Effect Transistor, the key block of modern Integrated Circuit (IC), is confronted with a serious challenge i.e. tremendously increasing power consumption in a chip consisting of billons of transistors. Transistors of novel architectures, such as multi-gate (e.g. FinFET) or gate-all-around (GAA) devices with high-k/metal gate (HKMG), are able to work properly at small supply voltage with lowered power consumption. Nevertheless, a physical limit of Boltzmann tyranny originating from basic thermodynamics theory renders the subthreshold swing (SS) of a Si-based transistor no less than 60 mV/dec at room temperature, which unfortunately leads to the reluctant reduction of power consumption in state-of-the-art transistors.
By integrating hafnium based ferroelectric materials in the HKMG process, so-called differential negative capacitances (NC) can be realized under certain conditions to amplify the surface potential of the channel, thus breaking through the traditional Boltzmann tyranny and obtaining a steeper SS for significantly improved switching behavior. Consequently, a smaller supply voltage can be employed for the operation of IC. It is worth noting that even some progress has been made in recent years, the exploration of novel ferroelectric materials in mainstream FinFETs is, however, still in the inception phase and as-fabricated devices generally show poor performance due to numerous challenges of materials and integration process.
In order to cope with these challenges and accomplish the goal of reduced power consumption and improved device performance simultaneously, researchers from Integrated Circuit Advanced Process Center (ICAC) of Institute of Microelectronics, Chinese Academy of Sciences (IMECAS) have developed new processes for the growth of ferroelectric Hafnium Zirconium Oxide (HZO) and integration in FinFETs etc. High performance NC p-FinFETs of different gate lengths featuring with an ultra-thin 3-nm-thick ferroelectric HZO are demonstrated.
In detail, in order to realize a low interface defect density of HZO/SiO2/Si, both the atomic-layer deposition (ALD) process and post-annealing process have been carefully modulated during the growth of ultra-thin HZO. Thanks to the fully depleted Fin channels under strong 3D gate control, low interface defect density of HZO/SiO2/Si and appropriate engineering of capacitance matching, as-fabricated FinFETs show greatly improved subthreshold swing (SS) values i.e. 34.5 mV/dec with 500 nm gate length (LG) and 53 mV/dec with 20 nm LG, and small hysteresis voltages i.e. ~9 mV with 500 nm LG and ~40 mV with 20 nm LG. The SS is much smaller than Boltzmann tyranny of 60 mV/dec and the hysteresis voltage is well controlled to an acceptable level. In addition, compared to that of conventional FinFETs with general HfO2, a prominent enhancement of driving current by 260% is also obtained for as-fabricated NC FinFETs. The ratio between Ion and Ioff is as high as 1.23×106. Taking ultra-steep SS, enhanced driving current and small hysteresis into account, as-fabricated NC FinFETs in this work pave a way for developing core transistors with almost identical performance while remarkably lowered power consumption in the future. The latest results have been published in a prestigious journal “IEEE Electron Device Letters” (DOI: 10.1109/LED.2019.2891364).
This work was financially supported by the National Science and Technology Major Project 02 and the National Key Research and Development Program.