TSMC, ARM announce first 16nm FinFET tapeout of big.LITTLE Cortex-A57 SoC | ExtremeTech
There are four distinct stages in semiconductor production.
1.
Test wafer. This is a proof-of-concept. It shows the underlying technology is capable of producing an advanced chip.
2.
Tape-out. "Taping out refers to the initial design of the chip having been completed for creation of the masks that will be used to print the actual chips, although further tweaks are likely as test production is carried out."[1]
3.
Risk production. "'Risk production' is used in the semiconductor industry to describe the first general availability of a new IC process, following the preceding test chip phase that manufacturers use to wring out a new technology."[2] In plain English, risk production refers to creating a few batches of wafers to determine yield and an opportunity to improve the process technology.
4.
Mass production.
4a.
Initial mass production. If there are serious problems with the process technology, yield per wafer can be as low as single digits to 30%.
A decent initial mass production yield is 50%.
4b.
Ramp up. Mature mass production yield is 95%.[3] The time between initial mass production (with relatively low yield) and mature mass production after ramp up (with high yield per wafer) is typically one to two years.
References:
1.
Apple and TSMC Reportedly Completing Designs for 20-nm A7 Chip With Early 2014 Availability - Mac Rumors
2.
EDA vendors roll out advances for 20 nm design - DSP-FPGA.com
3.
Report: Low yields force TSMC to revert to 8 inch wafers for Apple iPhone 6 fingerprint sensors
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6-core 16nm FinFET ARM Cortex-A57 chips spotted in the wild | SemiAccurate
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6-core 16nm FinFET ARM Cortex-A57 chips spotted in the wild
MWC 2014: Not just one, a full wafer of them fresh from the oven
Mar 3, 2014 by Charlie Demerjian
What do you get when you put a 6-core ARM A57 on TSMC’s 16nm FinFET process? A lot of pretty pictures and a really big bunch of test chips to play with too.
At MWC last week, SemiAccurate spotted a nice A57 wafer hidden away in the ARM booth. Not much was said about it other than 16nm, TSMC, and A57 cores all of which, “Taped-out February, 2014″. That means it is as fresh tasting as it is pretty.
If you look at the wafer below, it is pretty obvious that there are six cores on the die plus a bunch of other test structures. This is a test chip after all, and the purpose is to optimize the A57 core for the upcoming process, and given the time from tape-out, it is hot from the oven. This means the work on the process is still ongoing and likely far from done.
[My personal comment to explain a physical phenomenon: The different structures on the chip act as a diffraction grating, because the geometry is smaller than the wavelength of visible light. Hence, the spectrum of colors.]
Pretty, shiny FinFETs make big cores from small transistors
Why would you do something as complex as a multi-core A57 SoC that will never actually be a product? Remember ARM’s PoP IP? It takes a lot of work to get to the point of having an almost turnkey solution for licensees, and if a foundry does it right, it is a serious competitive advantage for them. In short this kind of thing is the homework that makes a licensee’s life easier. For the rest of us we get pretty pictures and SoCs with new cores faster. Hard to argue that one."
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TSMC, ARM announce first 16nm FinFET tapeout of big.LITTLE Cortex-A57 SoC | ExtremeTech
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TSMC, ARM announce first 16nm FinFET tapeout of big.LITTLE Cortex-A57 SoC
By Joel Hruska on February 25, 2014 at 11:45 am
TSMC and ARM have announced a further milestone on the road towards 16nm FinFET production, with the first successful tapeout of an asynchronous big.LITTLE SoC that pairs four Cortex-A53 cores with two Cortex-A57s. This follows the two company’s joint collaboration on a single Cortex-A57 core 10 months ago, and means that 16nm FinFET designs are moving towards fruition — though full production is still a little ways down the road.
For ARM, advancing an asynchronous big.LITTLE chip is a critical part of its strategy to drive adoption of its power reduction technology. The first generation big.LITTLE devices are all synchronous, meaning that companies like Samsung implemented four small cores alongside four large ones (typically a Cortex-A7/Cortex-A15 pairing). This made it easier to switch between operating modes — the operating system never saw more than four cores at any time, so it couldn’t become confused about which processors to run on which CPUs. A 4:2 pairing makes more sense from an optimization perspective where manufacturers may only want two cores for occasional burst activity and heavy lifting, but it requires more tuning on the OS front.
According to ARM, this new SoC more closely resembles the kind of test chip that a customer might actually build in a shipping product — though it’s still a test chip and not a commercial design. (article continues)"
